Takeshi Ishitsuka

Second-Harmonic Generation from an Interfacial Layer between Orientation Films and Liquid Crystal Layers of Nematic Liquid Crystal Cell

A second-harmonic generation (SHG) has been observed in a nematic liquid crystal cell containing highly polarized liquid crystal and orientation films with high polarization. No SHG is observed when a nonpolar liquid crystal is used regardless of the polarities of the orientation films used. The observed SHG is thought to originate from the ferroelectriclike layer, which comprises decomposed polar liquid crystals, at the interface between the orientation film and the liquid crystal layer.

Thermal stress destruction analysis in low-k layer by via-last TSV structure

Investigation of the thermo-mechanical stress by using finite element analysis (FEA) and the destruction verification with thermal cycle (TC) test were carried out. It was found that the back end of line (BEOL) dielectric layer near the through silicon via (TSV) was cracked in case of a RT-400 °C heat cycle. Thermo-mechanical stress concentration at the TSV landing area has been confirmed by the results of FEA simulation. Dielectric layer cracking was caused at interface between the dielectric layer and edge corner of the land metal (M1) contact pad connected with the TSV. And the slit voids at the TSV sidewall were observed on the area of insufficient of side coverage of the titanium (Ti) metal barrier liner at the TSV bottom. The BEOL deformation of the metal contact area was also clear that the low-k cracks tend to occur at non constraint condition of the TSV sidewall as the slit void. In this paper shows that the interface becomes free surface as non-constrained condition caused by poor liner coverage, and it was insufficient interface adhesion to suppress the thermal expansion deformation of copper. This study provides that low-k layer cracking can be avoided by adopting optimized stress dispersion design to the BEOL low-k/copper with TSV landing pad structure.

New developing process for PVCz holograms

The authors investigate a developing process for volume holograms consisting of poly-N- vinylcarbazole (PVCz), and achieve a new process that enables high diffraction efficiency, large holograms and uniform quality. Conventionally PVCz holograms are developed by two sequential dipping processes: first into good solvent, then into poor solvent. When a swollen PVCz film is dipped into poor solvent, PVCz molecules precipitate into small grains, and micro-gaps between grains are formed corresponding to the degree of swelling. As the result of the difference in swelling between highly exposed and low exposed areas, refractive index modulation appears. In this process, it is difficult to obtain a large hologram, because the upper area dries more than the lower area when the swollen film is carried to poor solvent. Based on the investigation above, the authors found a new process where the holograms are developed by a single dipping process into a mixture of volatile good solvent and nonvolatile poor solvent. The hologram film swells with the mixture, and is then carried out slowly from the tub. The solvent mixture in the film becomes poor solvent, rich and small grains are formed, because a good solvent evaporates more quickly than a poor solvent. With this new process all areas of a hologram plate can be developed under same conditions, so large holograms with uniform quality become possible.

Study of MOSFET thermal stability with TSV in operation temperature using novel 3D-LSI stress analysis

A large thermal-mechanical stress caused by the mismatch of thermal expansion coefficients (CTEs) between the copper and silicon substrate occurs in the active area of the stacked 3D device using the through-silicon via (TSV). Therefore, the study of TSV-induced stress is of fundamental importance in our understanding of the keep-out zone (KOZ). We investigated the metal-oxide-semiconductor field-effect transistor (MOSFET) thermal stability of a device operated by combining Technology Computer-Aided Design — Simulation Program with Integrated Circuit Emphasis (TCAD-SPICE) stress analysis and an actual ring oscillator circuit (ROSC) nearby TSVs. The MOSFET drain current (Id) fluctuates in response to the behavior of the Si stress caused by the TSVs. However, it was found that the simulation and test measurement results showed that the KOZ becomes smaller because the electric charge/discharge is canceled in the case of a p/n MOS inverter circuit. This study showed the importance of the design of the KOZ, which includes the temperature fluctuation phenomenon in a real integrated circuit device operation.