Takeyuki Sone
Sony Broadcast & Professional Research Laboratories
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Featured researches published by Takeyuki Sone.
international electron devices meeting | 2007
Katsuhisa Aratani; Kazuhiro Ohba; Tetsuya Mizuguchi; Shuichiro Yasuda; Tsunenori Shiimoto; Tomohito Tsushima; Takeyuki Sone; K. Endo; Akira Kouchiyama; Satoshi Sasaki; A. Maesaka; N. Yamada; Hiroaki Narisawa
We report a novel nonvolatile dual-layered electrolytic resistance memory composed of a conductive Cu ion activated layer and a thin insulator for the first time. An ON/OFF mechanism of this new type memory is postulated as follows: Cu ions pierce through the insulator layer by applied electric field, the ions form a Cu conductive bridge in the insulator layer, and this bridge dissolves back to the ion activated layer when the field is reversed. The 4 kbit memory array with 1T-1R cell structure was fabricated based on 180 nm CMOS process. Set/reset pulses were 5 ns, 110 muA and 1 ns, 125 muA, respectively. Those conditions provide large set/reset resistance ratio of over 2 orders of magnitude and satisfactory retention. Essential characteristics for high capacity memories including superb scalability down to 20 nmphi, sufficient endurance up to 107 cycles and preliminary data for 4-level memory are also presented. These characteristics promise the memory being the next generation high capacity nonvolatile memory even before the scaling limitation of flash memories is encountered.
Journal of Applied Physics | 2005
Tetsuya Yamamoto; Hiroshi Kano; Yutaka Higo; Kazuhiro Ohba; Tetsuya Mizuguchi; Masanori Hosomi; Kazuhiro Bessho; Minoru Hashimoto; Hiroyuki Ohmori; Takeyuki Sone; Keitaro Endo; Shinya Kubo; Hiroaki Narisawa; Wataru Otsuka; Nobumichi Okazaki; Makoto Motoyoshi; Hajime Nagao; Tsutomu Sagara
The reliability in magnetoresistive random access memory (MRAM) write operation was investigated for both toggle and asteroid memory chips developed with 0.18μm CMOS process. Thermally activated magnetization reversal, being the dominant origin of the intrinsic write error, was studied theoretically and experimentally. For asteroid MRAM, the bit line or word line disturbing error on half selected bits was proved to have significant effect on the write operation margin, even in the ideal case free from bit-to-bit switching field distribution and the hysteresis loop shift. For toggle MRAM, on the other hand, the dominant origin of the error occurs for selected bits, although its impact is much smaller than in the case of asteroid MRAM. As was expected from the estimation based on the single domain model, more than 10mA operation margin with the error rate of <10−9, which is sufficiently small for semiconductor IC memory, was achieved for the toggle MRAM.
Journal of Applied Physics | 2002
Atsushi Matsuzono; Shoji Terada; Hiroaki Ono; Akio Furukawa; Takeyuki Sone; Satoshi Sasaki; Y. Kakihara; Y. Takeda; N. Chiyokubo; H. Matsuki
Shielded current perpendicular to the plane (CPP) spin valve heads with about 20 Gbit/in.2 dimensions were fabricated and tested both quasistatically and dynamically. Dual synthetic spin valves with 2.3 mΩ μm2 of resistivity change and area product (dRA) was used. Quasistatic tests were conducted to determine the current efficiency loss caused by the specific CPP head structure. Dynamic tests were performed to examine the flux efficiency of the readback process in the spin valve element, in order to confirm the calculation results which take into account the increase of effective anisotropy field caused by the circular sense current field. Output voltage of about 260 μV (peak to peak) was successfully obtained from the dynamic tests. Finite element modeling analysis of current distribution and temperature rise, together with degradation experiments with excessive sense current, was conducted to predict the maximum allowable current density in the 200 Gbit/in.2 dimension, where read track width and stripe ...
symposium on vlsi technology | 2017
Shuichiro Yasuda; Kazuhiro Ohba; Tetsuya Mizuguchi; Hiroaki Sei; Masayuki Shimuta; Katsuhisa Aratani; Tsunenori Shiimoto; Tetsuya Yamamoto; Takeyuki Sone; Seiji Nonoguchi; Jun Okuno; Akira Kouchiyama; Wataru Otsuka; Keiichi Tsutsui
This paper demonstrates a cross point Cu based Resistive Random Access Memory (Cu-ReRAM) technology suitable for Storage Class Memory (SCM) applications. Two key technologies have been developed for large capacity of 100Gb-class SCM with 100 ns program speed and 10M cycles of program endurance. One is tight resistance distributions of Cu-ReRAM by inserting a barrier layer to prevent excess intermixing. The other is a novel Boron and Carbon (BC) based Ovonic Threshold Switch (OTS) selector which meets requirements for large cross point arrays with low leakage current, low threshold voltage variability, and high endurance.
Archive | 2002
Kazuhiro Ohba; Kazuhiko Hayashi; Hiroshi Kano; Kazuhiro Bessho; Tetsuya Mizuguchi; Yutaka Higo; Masanori Hosomi; Tetsuya Yamamoto; Hiroaki Narisawa; Takeyuki Sone; Keitaro Endo; Shinya Kubo
Archive | 2003
Tetsuya Mizuguchi; Masanori Hosomi; Kazuhiro Ohba; Kazuhiro Bessho; Yutaka Higo; Tetsuya Yamamoto; Takeyuki Sone; Hiroshi Kano
Archive | 2005
Masanori Hosomi; Kazuhiro Bessho; Kazuhiro Ohba; Tetsuya Mizuguchi; Yutaka Higo; Takeyuki Sone; Tetsuya Yamamoto; Hiroshi Kano
Archive | 2003
Kazuhiro Ohba; Masanori Hosomi; Kazuhiro Bessho; Tetsuya Mizuguchi; Yutaka Higo; Tetsuya Yamamoto; Takeyuki Sone; Hiroshi Kang
Archive | 2003
Takeyuki Sone; Kazuhiro Bessho; Masanori Hosomi; Tetsuya Mizuguchi; Kazuhiro Ohba; Tetsuya Yamamoto; Yutaka Higo; Hiroshi Kano
Archive | 2002
Kazuhiro Ohba; K. Hayashi; Hiroshi Kano; Kazuhiro Bessho; Tetsuya Mizuguchi; Yutaka Higo; Masanori Hosomi; Tetsuya Yamamoto; Hiroaki Narisawa; Takeyuki Sone; Keitaro Endo; Shinya Kubo