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IEEE Transactions on Semiconductor Manufacturing | 2015

Pattern-Independent PMD Layer Planarization by Controlling its Volume Before CMP

Tomoyasu Kakegawa; Takuya Futase

We achieved excellent planarization for a pre-metal dielectric (PMD) layer regardless of its pattern density distribution by making the distribution uniform before chemical mechanical polishing (CMP) without any stopper layer. The distribution control was done by lithography using a checkered reticle on the high-density PMD area followed by etching of the PMD layer to uniformize the CMP rates at both areas. After this planarization, the PMD layer was flattened in the local and global regions. The PMD step-height within chip was approximately 8 nm (approximately 1% of PMD height), which is a variation of less than one tenth compared with conventional planarization, and the non-uniformity of PMD thickness within wafer was approximately 2%. The planarized PMD layer suppressed the defocusing in lithography for contact hole formation on the layer, thus dramatically reducing contact-open failures in a chip of approximately 50 × 110 nm in diameter with 620-nm high-contact holes. The number of defects was one-thousandth that of a conventionally planarized PMD layer.


Archive | 2014

Air Gaps Structures for Damascene Metal Patterning

Yuji Takahashi; Takuya Futase; Yoko Furihata; Satoshi Kamata


Archive | 2014

BARRIER LAYER STACK FOR BIT LINE AIR GAP FORMATION

Takuya Futase; Katsuo Yamada; Tomoyasu Kakegawa; Noritaka Fukuo; Yuji Takahashi


Archive | 2017

Contact Plug Extension for Bit Line Connection

Shunsuke Watanabe; Kiyokazu Shishido; Yuji Takahashi; Takuya Futase; Eiichi Fujikura; Noritaka Fukuo; Hiroto Ohori; Kotaro Jinnouchi; Hiroki Asano


Archive | 2016

Silicided bit line for reversible-resistivity memory

Kan Fujiwara; Takuya Futase; Toshihiro Iizuka; Shin Kikuchi; Yoichiro Tanaka; Akio Nishida; Christopher J. Petti


Archive | 2016

Conductive Lines with Protective Sidewalls

Noritaka Fukuo; Takuya Futase; Katsuo Yamada; Yuji Takahashi; Tomoyasu Kakegawa


Archive | 2014

Contact Hole Collimation Using Etch-Resistant Walls

Tomoyasu Kakegawa; Takuya Futase; Katsuo Yamada; Keita Kumamoto; Hirotada Tobita


Archive | 2014

Early Bit Line Air Gap Formation

Hiroto Ohori; Takuya Futase; Yuji Takahashi; Toshiyuki Sega; Kiyokazu Shishido; Kotaro Jinnouchi; Noritaka Fukuo


Archive | 2014

NAND Flash Memory Integrated Circuits and Processes with Controlled Gate Height

Eiichi Fujikura; Susumu Okazaki; Takuya Futase; Fumiaki Toyama; Hiroaki Koketsu


Archive | 2014

Buried Etch Stop Layer for Damascene Bit Line Formation

Yuji Takahashi; Takuya Futase; Noritaka Fukuo; Katsuo Yamada; Tomoyasu Kakegawa

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