Tamer Coskun

A single-exposure approach for patterning 45nm flash/DRAM contact hole mask

Contact hole (CH) patterning for DRAM/Flash presents a key challenge for design rule below 50nm due to aggressive low-k1 conditions common in the leading DRAM/Flash memory designs. Combining optical proximity corrections (OPC) to the mask and optimized illumination has become an important part of production-worthy lithography processes for the 65nm node. At k1<0.31, both resolution and imaging contrast can become severely limited at NA<0.85 with some commonly available off-axis illumination sources. Hyper-NA and immersion lithography with polarized illumination capability can significantly increase the process latitude and is indispensable for manufacturing at sub-50nm design rule and beyond. In this work, we describe our single-exposure approach for patterning Flash/DRAM contact-hole patterns with 120nm minimum pitch (and 60nm CH target CD). We use 6% attPSM dark-field mask both in simulations and for wafer exposures on ASML XT:1700i at NA=1.2. We begin with illumination source optimization using full vector high-NA simulation with (unpolarized and Y polarized illumination) a production resist stack and taking into account during the optimization all manufacturability requirements for the corresponding diffractive optical element (DOE) that produces the optimized source at the mask level. Using the optimized source, model-based OPC treatment was performed, which includes scattering bars (SB) placement using IMLTM technology and model-based CH feature biasing (MOPC) to achieve the optimum pattern printing fidelity in-focus and process latitude. To further increase of the depth of focus (DOF) for common process window (CPW) from 150nm to >250m, we used the focus scan (or, focus drilling) technique which is available in todays leading 193nm scanners. Our results showed that, for the 120nm minimum pitch Flash CH patterns used, hyper-NA (NA>1) and immersion lithography (ASML XT:1700i platform was used in both simulation and scheduled for wafer exposures) is necessary, together with optimized illumination and model based OPC treatment, to achieve a yielding baseline process (common process window with DOF ~100nm). We also demonstrate that polarized illumination can significantly enhance the overall imaging performance, i.e., worst-case DOF can be increased >25% with optimized source, which is limited by the dense pitch CH arrays for this particular Flash CH pattern. With focus scan enabled for imaging, we show that the worst-case individual DOF can be easily doubled (from 150nm to >300nm) and EL at best focus (BF) remains >10% even at the largest focus range settings (400nm). The common process window decreased as focus scan range was increased, indicating that to maintain optimum common process window, MOPC treatment must be also performed under the same focus scan conditions. Patterning optimization (from illumination optimization to OPC) with focus scan enabled shows excellent promise as a single-exposure solution for patterning this 45nm Flash CH pattern and beyond.

Patterning 45nm flash/DRAM contact hole mask with hyper-NA immersion lithography and optimized illumination

Patterning contact-hole mask for Flash/DRAM is probably one of the most challenging tasks for design rule below 50nm due to the extreme low-k1 printing conditions common in the memory designs. When combined with optical proximity corrections (OPC) to the mask, using optimized illumination has become a viable part of the production lithography process for 65nm node. At k1<0.31, both resolution and imaging contrast can become severely limited by some of the current imaging tools with NA<0.85 and using standard illumination sources. Hyper-NA immersion lithography increases the process latitude and is therefore expected to become more indispensable for manufacturing under extreme low-k1 conditions for sub-50nm design rule. In this work, we describe our process optimization approach for patterning Flash/DRAM contact-hole patterns with 130nm, 120nm, and smaller minimum pitch design rules. Here we use 6% attPSM mask for simulation and actual exposure in ASML XT 1400i (NA=0.93) and 1700i (NA=1.2) respectively. We begin with the illumination source optimization using full vector high-NA calculation (VHNA) with production resist stack and all manufacturability requirements for the source shaping diffractive optical element (DOE) are accounted for during the source optimization. Using the optimized source, IMLTM technology based scattering bars (SB) placement together with model based OPC (MOPC) are applied to the original contact-hole design. In-focus printing and process latitude simulations are used to gauge the performance and manufacturability of the final optimized process, which includes the optimized mask, optimized source and required imaging settings. Our results show that for the 130nm pitch Flash contact-hole patterns, on ASML XT 1400i at NA=0.93, both optimized illumination source and immersion lithography are necessary in order to achieve manufacturability. The worst-case depth of focus (DOF) before SB and MOPC is 100-130nm at 6% EL, without common process window (PW) and with MOPC, the worst-case DOF is >200nm at 6% EL. The latter is in excellent agreement with the wafer results from ASML XT 1400i, and the predicated CDs match well with the measured at isolated, medium and dense pitch contact-holes to within 5nm. For the 120nm pitch Flash contact patterns, ASML XT 1700i at NA=1.2 must be used, together with optimized illumination source, to achieve the same or better process latitude (worst-case DOF at 6% EL), and for the Flash pattern used, further enhancements of >20% in DOF @ 6% EL using Y linear polarization can be achieved, before SB and MOPC. With preliminary SB and MOPC, the worst-case DOF @ 6% EL is increased from 100nm to 150nm and with common PW for all critical CDs, from isolated to dense contact-holes. Two examples of customized polarizations are considered in the above simulations to demonstrate the effects of polarizations on imaging and process latitude for pattern specific contact-holes. The pros and cons of the current patterning solution are discussed and compared with alternatives.

Precision process calibration and CD predictions for low-k1 lithography

Leading resist calibration for sub-0.3 k1 lithography demands accuracy <2nm for CD through pitch. An accurately calibrated resist process is the prerequisite for establishing production-worthy manufacturing under extreme low k1. From an integrated imaging point of view, the following key components must be simultaneously considered during the calibration - high numerical aperture (NA>0.8) imaging characteristics, customized illuminations (measured vs. modeled pupil profiles), resolution enhancement technology (RET) mask with OPC, reticle metrology, and resist thin film substrate. For imaging at NA approaching unity, polarized illumination can impact significantly the contrast formation in the resist film stack, and therefore it is an important factor to consider in the CD-based resist calibration. For aggressive DRAM memory core designs at k1<0.3, pattern-specific illumination optimization has proven to be critical for achieving the required imaging performance. Various optimization techniques from source profile optimization with fixed mask design to the combined source and mask optimization have been considered for customer designs and available imaging capabilities. For successful low-k1 process development, verification of the optimization results can only be made with a sufficiently tunable resist model that can predicate the wafer printing accurately under various optimized process settings. We have developed, for resist patterning under aggressive low-k1 conditions, a novel 3D diffusion model equipped with double-Gaussian convolution in each dimension. Resist calibration with the new diffusion model has demonstrated a fitness and CD predication accuracy that rival or outperform the traditional 3D physical resist models. In this work, we describe our empirical approach to achieving the nm-scale precision for advanced lithography process calibrations, using either measured 1D CD through-pitch or 2D memory core patterns. We show that for ArF imaging, the current resist development and diffusion modeling can readily achieve ~1-2nm max CD errors for common 1D through-pitch and aggressive 2D memory core resist patterns. Sensitivities of the calibrated models to various process parameters are analyzed, including the comparison between the measured and modeled (Gaussian or GRAIL) pupil profiles. We also report our preliminary calibration results under selected polarized illumination conditions.