Tamotsu Kasai
Osaka Prefecture University
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Featured researches published by Tamotsu Kasai.
IEEE Transactions on Computers | 1976
Teruo Okuda; Eiichi Tanaka; Tamotsu Kasai
In this paper we propose a new method for correcting garbled words based on Levenshtein distance and weighted Levenshtein distance. We can correct not only substitution errors, but also insertion errors and deletion errors by this method. According to the results of simulation on nearly 1000 high occurrence English words, higher error correcting rates can be achieved by this method than any other method tried to date. Hardware realization of the method is possible, though it is rather complicated.
IEEE Transactions on Information Theory | 1976
Eiichi Tanaka; Tamotsu Kasai
Block codes are constructed that are capable of simultaneously correcting e or fewer synchronization errors in t consecutive words, for any t \geq 2e + 1 , and s or fewer substitution errors in eachof t - 1 or fewer of these words under the condition that there exists at least one ungarbled word among the t consecutive words. Also, some new extensions of the A_{n}^{c} codes of Calabi and Hartnett are presented under the condition that synchronization and substitution errors do not coexist in the t consecutive words.
design automation conference | 1983
Kunio Fukunaga; Shoichiro Yamada; Harold S. Stone; Tamotsu Kasai
This paper deals with the problem of automated placement of electronic components in a circuit layout by using a graph-space approach. In this approach, the relationships of connections among modules in a given electronic circuit are represented by a hypergraph. Then by using a graph-space approach, the vertices (representing the modules) are mapped into the graph space such that the distance between vertices in the space reflects the weights (the number of wires) of edges between vertices of the original hypergraph. On the basis of this placement in graph-space, the modules are assigned to grids on the printed-circuit board so as to minimize the total wire length. Simulation results show this technique yields a better assignment than the one derived from a hand-optimized layout and from an accepted automated-design method.
International Journal of Electronics | 1986
Shojiro Yoneda; Ikuo Nakamura; Itsuo Sasaki; Tamotsu Kasai
A new switched-capacitor realization of a non-recursive filter based on the digital filter theorem is proposed. A switched-capacitor realization of the delay circuit is described first. A switched-capacitor coefficient multiplier and adder are based on the integral feedback capacitance circuit. This circuit has the feature that the voltage across the integral feedback capacitance is used for the output voltage, whereas, in an ordinary circuit, the output voltage is used at the output terminal of an operational amplifier. Agreement between experimental and theoretical values is confirmed.
international symposium on circuits and systems | 1988
Itsuo Sasaki; Kenji Matsui; Shojiro Yoneda; Tamotsu Kasai
A novel switched-capacitor discrete Walsh transform circuit is proposed. The Walsh hardware transformation is improved in simplicity by using the proposed circuit, and this circuit has a speed advantage because of analog processing. Furthermore, a switched-capacitor inverse Walsh transform circuit is constructed. A switched-capacitor sequence filter is also proposed which combines the Walsh transform circuit and its inverse.<<ETX>>
International Journal of Electronics | 1988
Shojiro Yoneda; Y. Abe; L Sasaki; Tamotsu Kasai
ABSTRACT The realizations of switched-capacitor filter based on the digital filter and their problems are indicated. There are two types of filters, non-recursive and recursive. For the switched-capacitor realization of non-recursive, an improvement is given, and for that of recursive, a limitation under the circuit configuration using discrete parts is shown
International Journal of Electronics | 1985
Shinji Masuda; Shojiro Yoneda; Tamotsu Kasai
ABSTRACT A general-purpose analogue signal processor is presented in which all operations are performed in a charge domain. The processor can be customized to each application according to an instruction program. The processor is composed of amplifiers, analogue switches, capacitors and a memory. Charge-domain processing techniques and a calibration technique are used to reduce the requirement for a capacitor precision-ratio. An application to bandpass filtering is demonstrated.
Proceedings of the 1977 annual conference on | 1977
Kunio Fukunaga; Tamotsu Kasai
The computer storage consists of a large, slow main storage and a small, fast storage called a buffer, which is integrated into the CPU. A proper management of data in the two storages can satisfy the desire for large and fast memory. The performance of this system is significantly influenced by the hit rate, which is defined as the probability of finding the data wanted for a fetch in buffer storage. This paper discusses an approach of representing the degree of association between variables for a given program and describes an associative assignment of program variables into main storage in order to imp rove the hit rate. As a result of the simulation, this association mehtod provides a good indication of performance.
Systems and Computers in Japan | 1988
Eiichi Tatsumi; Kunio Fukunaga; Tamotsu Kasai
The determination of the matching feature points in the left and the right images is one of the important problems. As one means to cope with this problem, a method has been presented in which the continuous feature points are approximated by edges, and the matching pair is determined by comparing the edge-line structures of the two images. This paper presents a method which handles not only the edge-lines but also the arcs in a similar way as the features of the image
International Journal of Electronics | 1988
Itsuo Sasaki; Shojiro Yoneda; Tamotsu Kasai
An analogue window function circuit is realized by using switched-capacitor techniques. In order to verify the effect of this window, a novel switched-capacitor analogue discrete Fourier analyser is proposed. The window function circuit is included in this analyser as the ratios of capacitances. This switched-capacitor discrete Fourier analyser is very simple in construction, namely, only two elemental circuits based on the integral feedback capacitance circuit are connected in series. Agreement between the experimental and the theoretical values is confirmed.