Tanja Van Achteren

Systematic data reuse exploration methodology for irregular access patterns

Efficient use of an optimized custom memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in embedded data dominated applications. Only recently effective formalized techniques to deal with this specific task have been addressed. They work well for homogeneous signal access patterns but cannot handle other cases. In this paper we will extend and parameterize the design space and establish heuristics for an efficient exploration, such that better results in terms of area and power can be achieved for applications where holes are present in the signal access pattern. The extended methodology will be illustrated for several real-life image processing algorithms.

Search space definition and exploration for nonuniform data reuse opportunities in data-dominant applications

Efficient exploitation of temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in embedded data dominated applications. The effective use of an optimized custom memory hierarchy or a customized software controlled mapping on a predefined hierarchy is crucial for this. Only recently have effective systematic techniques to deal with this specific design step begun to appear. They are still limited in their exploration scope. In this paper we construct the design space by introducing three parameters which determine how and when copies are made between different levels in a hierarchy, and determine their impact on the total memory size, storage-related power consumption, and code complexity. Strategies are then established for an efficient exploration, such that cost-effective solutions for the memory size/power trade-off can be achieved. The effectiveness of the techniques is demonstrated for several real-life image processing algorithms.

Statistical Performance Analysis and Estimation for Parallel Multimedia Processing

When parallelizing complex multimedia processing on multiple processors, the stochastic timing behavior should be carefully studied. Although there are already many papers on the performance analysis of stochastic parallel system, they are not targeted on multimedia processing. In this paper, first we study H.264/AVC encoder (running on x86) and QSDPCM encoder (running on TI TMS32C62) to characterize important aspects of the stochastic timing behavior in complex multimedia processing applications. It is shown that the variation and correlation are indeed very significant. In order to make systematic analysis feasible, we apply Stochastic Timed Marked Graph (STMG) as a formal model to capture essential timing related behaviors of parallel multimedia processing systems. Then, we show how the local timing variations and correlations interact and propagate to the global timing behavior; from this we conclude general parallelization guidelines. Furthermore, we develop an analytical performance estimation technique to derive the probability distribution of timing behavior for parallel multimedia processing systems that have correlated stochastic timing behaviors inside. The estimation technique is based on principal component analysis and approximations.

Optimizing a 3D image reconstruction algorithm: investigating the interaction between the high-level implementation, the compiler and the architecture

Digital signal processing and multimedia workloads will be a dominant workload for computer based systems in the near future. In this paper, we evaluate the performance of an important media application, namely a relatively new 3D image reconstruction algorithm, on two platforms: a DSP processor (Texas Instruments TMS320C6701) and a high-performance general-purpose microprocessor (Alpha 21164). Prior to evaluating the performance of both architectural paradigms---very long instruction word (VLIW) versus an in-order superscalar organization---we optimized the algorithm by applying algorithmic optimizations as well as implementation-dependent optimizations. For the VLIW architecture, we obtained a 12X speedup for a 465x320 image; on the Alpha 21164, a 4X speedup was obtained. Thanks to this high speedup, this 3D image reconstruction algorithm becomes useful for real-time use. Next to evaluating the various optimizations, we also discuss the implications of these optimizations on the performance of various architectural structures, such as the branch predictor and the memory hierarchy.

Data Transfer and Storage Exploration in Programmable Architectures

This introductory chapter will contain the problem context that we focus on, including the target application domain and architectural style. Then the global approach for reducing the cost of data access and storage is described. Next, a summary is provided of all the steps in the Data Transfer and Storage Exploration (DTSE) script. Finally the content of the rest of the book is briefly outlined.

Related Compiler Work on Data Transfer and Storage Management

In this chapter, an extensive summary is provided of the main related compiler work in the domain of this book. It is organized in a hierarchical way where the most important topics receive a separate discussion, with pointers to the available literature. Wherever needed, a further subdivision in subsections or paragraphs is made.

Storage Cycle Budget Distribution and Access Ordering

In many cases, a fully customized (on-chip) memory architecture can give superior memory bandwidth and power characteristics over traditional hierarchical memory architecture including data caches. This is especially so when the application is very well analyzable at compile-time. In an embedded context this is typically quite well achievable because the application (set) to be mapped is usually fully fixed and the on-chip memory organisation can be at least partly tuned towards this application (set).

System-Level Storage Estimation with Partially Fixed Execution Ordering

Estimators at the system-level are crucial to help the designer in making global design decisions and trade-offs. For data-dominant applications in the multi-media and telecom domains, the system-level description is typically characterized by large multi-dimensional loop nests and arrays. A major aspect of system cost related to such codes is due to the data transfer and storage (DTS) aspects, as motivated in chapter 1. Cost models for the amount of area per memory cell or the energy consumption per access for a given memory plane size can be obtained from vendors. However, in order to identify the amount of memory accesses or data transfers and the required memory size, automatable estimation techniques are required. Effective approaches for this are described in this chapter.

Global Loop Transformation Steering

As motivated, the reorganisation of the loop structure and the global control flow across the entire application is a crucial initial step in the DTSE flow Experiments have shown that this is extremely difficult to decide manually due to the many conflicting goals and trade-offs that exist in modern real-life multi-media applications. So an interactive transformation environment would help but is not sufficient. Therefore, we have devoted a major research effort since 1989 to derive automatic steering techniques in the DTSE context where both “global” access locality and access regularity are crucial.

Cache Optimization Methodologies and Automation

Architectural techniques for reducing cache misses are expensive to implement and they do not have a global view of the complete program which limits their effectiveness. Thus compiler optimizations are the most attractive alternative which can overcome both the above shortcomings of a hardware implementation. In this chapter, we will investigate the current state-of-the-art in compiler optimizations for caching. Afterwards, we propose a stepwise methodology which allows a designer to perform a global optimization of the program for a given cache organization. Then each of the main cache related steps will be studied in more detail including both problem formulations and techniques to solve them. The effectiveness of these automatable techniques will be substantiated by realistic demonstrators.