Tanvir Zaman Khan

Comparative Performance Analysis of Hamming, Hanning and Blackman Window

In the emerging field of medical image processing, computer vision, pattern recognition and other digital signal processing applications, window technique is vastly used. A window function is a mathematical function that is zero-valued outside of some chosen interval. When another function is multiplied by a window function, the product is also zero-valued outside the interval. In this paper, the performance of Hamming, Hanning and Blackman window have been mainly compared considering their magnitude response, phase response, equivalent noise bandwidth, sidelobe transition width, response in time and frequency domain using MATLAB simulation. To observe the responses, a FIR filter of low pass, high pass, band pass and band stop type have been designed and encountered them with each parameters stated above. The results that have been found is as same as its to be as stated in the theory. Comparing simulation results of different window, this paper has found Blackman window with best performance among them which is also expected from the theory. These windows have also been encountered with speech signal using MATLAB simulation and found the same expected result.

Iris image compression using wavelets transform coding

Iris recognition system for identity authentication and verification is one of the most precise and accepted biometrics in the world. Portable iris system mostly used in law enforcement applications, has been increasing more rapidly. The portable device, however, requires a narrow-bandwidth communication channel to transmit iris code or iris image. Though a full resolution of iris image is preferred for accurate recognition of individual, to minimize time in a narrow-bandwidth channel for emergency identification, image compression should be used to minimize the size of image. This paper has investigated the effects of compression particularly for iris image based on wavelet transformed image, using Spatial-orientation tree wavelet (STW), Embedded Zero tree Wavelet (EZW) and Set Partitioning in hierarchical trees (SPIHT), to identify the most suitable image compression. In this paper, Haar wavelet transform is utilized for image compression and image decomposition, by varying the decomposition level. The results have been examined in terms of Peak signal to noise ratio (PSNR), Mean square Error (MSE), Bit per Pixel Ratio (BPP) and Compression ratio (CR). It has been evidently found that wavelet transform is more effective in the image compression, as recognition performance is minimally affected and the use of Haar transform is ideally suited. CASIA, MMU iris database have been used for this purpose.

Reconfigurable architecture design of FIR and IIR in FPGA

At the modern world digital signal processing (DSP) has turned into an enormously vital subject. A fundamental aspect of the digital signal processing is filtering. Filtering is a selective system which passes a certain range of frequency and attenuating the others frequency. Digital filtering is a powerful sector of DSP related works. A digital filter is a system which performs mathematical operations on a sampled or discrete time variant signal to shrink or enhance assured aspects of that signal. Digital filters are classified into finite impulse response (FIR) and infinite impulse response (IIR), which are based on the duration of the impulse response. FIR is a stable system and there is no feedback, but IIR has a feed forward path. This paper mainly focuses on the design of FIR and IIR filters of different forms like direct form or transposed of direct form in FPGA. FPGA is a system which can be used to implement the logical function because of its cost-effective properties. The proposed design algorithm of FIR and IIR is modeled in HDL and after the logically verified synthesize in the XST synthesis tool. The design performance of FIR and IIR is analyzed through the timing diagrams summary (time delay, minimum execution period etc.), HDL synthesis report and device utilization summary.

Fast and efficient iris segmentation approach based on morphology and geometry operation

This paper presents a novel and robust method for pupil and iris boundary localization based on morphological and geometrical operation. This proposed method localizes the iris and pupil center in several stages. In the proposed algorithm Otsu threshold value, median filter, image complement, contact labeling and manual tracking are used for robust detection of the pupil. Otsu threshold is used for picking threshold value in order to determine the right binary image. Then edge point is used for the pupil boundary localization. The use of geometrical operation helps in better iris localization. Its performance does not degrade in case of seriously or partially affected eye images with eyelids and eyelashes. The proposed scheme has been tested on iris image databases like: CASIA-IrisV1 and CASIA-IrisV3. Experimental result demonstrates the supremacy of the proposed scheme in comparison with some other existing methods.

FPGA implementation of high performance Fast Page Mode dynamic random access memory

A digital system frequently requires memory for storage. To facilitate this requirement, FPGAs offer different types of memory, ranging from block RAM, a highly distributed RAM in the form of the multiple LUTs, right down to the storage of data in the flip-flops. However, unlike the conventional RAMs, dynamic random access memory (DRAM) is best suited for larger volumes of memory, because it permits complex yet advanced levels of integration, occupies less space in motherboard due to reduced feature size, and more importantly, it is inexpensive. Dynamic RAMs evolved from the earliest 1- kilobit (KB) generation to the modern 1-gigabit (GB) generation through the advances and developments in not only semiconductor process but also circuit design technology. This paper proposes resistor transistor logic (RTL) design of the firstgeneration and second-generation high performance (Fast Page Mode) dynamic random access memory. The simulation diagram was experimented using the Verilogger Test bench pro 6.5 software. The timing as well as device utilization summary has been presented in this paper and compared for both normal and fast page mode DRAM. For fast page mode DRAM, the combinational path delay was less compared to the first generation DRAM.