Tapas Nandy

Programmable high frequency RC oscillator

Conventional RC oscillators, though offer inexpensive components as resistors and capacitors, are not suitable for frequencies beyond few MHz. Here, a VCO based RC oscillator is proposed, where the output frequency can be programmed finely with digital codes over range of higher frequencies on the fly. In this architecture, divided output frequency of a VCO is compared precisely against an external RC time-constant at regular calibration interval and the VCO frequency is adjusted. The calibration rate can be adjusted by programmable choice of capacitor, to avoid any beat frequency with any system requirement. The circuit is designed and fabricated in a 0.18/spl mu/m technology for low voltage operation.

A low power 1.2Gbps sync-less integrating PWM receiver

A PWM receiver, without using a PLL or DLL, is proposed in this paper. This receiver does not need any synchronization (sync) bit sequence for locking on to the incoming data rate. No requirement of sync bits increases not only link throughput, but also reduces overall link power by allowing quick burst-sleep-burst transitions. A PWM bit symbol is decoded by time-to-voltage conversions of PWM major and minor durations followed by a comparison between them. Three such decoders are used in a time interleaved fashion to extract three consecutive PWM bits to achieve 1.2Gbps bit rate. Jitter tolerance measurement shows a high frequency jitter tolerance of 0.45UI at 1.2Gbps. This PWM receiver is fabricated in 40nm bulk CMOS process. It consumes 5.5mW and occupies an area of 0.0389mm2.

Self-Induced Supply Noise Reduction Technique in GBPS Rate Transmitters

In high speed link transmitters, one major contributor of jitter is the data-dependant switching of the transmitters. Such switching leads to oscillations in the supply R-L-C network. This paper presents an area-efficient way to reduce this supply noise by shifting the switching beyond the resonance frequency of the supply network, irrespective of the data-pattern. This scheme is implemented in HDMI transmitter in 65nm technology.

HDMI transmitter in 32nM technology using 28Å MOS

The output driver of the HDMI transmitter is designed in 32nM using MOS of 28 Å gate oxide thickness. These MOS transistors are capable of handling 1.8v only. The circuit protects the MOS transistors exposed to 3.3v at the receiver termination, when the transmitter is power on, as well as, when it is power off. The area of the implemented HDMI Transmitter physical layer is 0.283mm2 and power consumption is 12mW @ 2.22Gbps (740Mbps/Channel) as seen on silicon.

Zero power 4.95Gbps HDMI transmitter

The HDMI open drain transmitter is designed to harvest power from the receiver, through the termination impedances during signaling. There is no local power supply needed at the transmitter side, neither any power is taken from the receiver apart from whatever power comes out of it during standard signaling. The zero power HDMI Transmitter capable of datarate 4.95Gbps, i.e. 1.65Gbps per Channel is designed in 65nm technology.

A 8 Gbps blind oversampling CDR with frequency offset compensation over infinite burst

This paper presents a 8 Gbps high jitter tolerance (JTOL) corner-frequency hybrid CDR that employs blind oversampling phase detector in conjunction with digital proportional integral controller (PIC) for phase/frequency tracking with +/-4000ppm frequency offset compensation over infinite burst. Need of the elasticity buffer has been obviated by using a method of time-varying divider ratios in word-clock generation. Analytical treatment of the CDR dynamics and insight into its JTOL are also presented. Short lock time and tracking over infinite burst make this CDR reusable across applications requiring either burst or continuous mode support. The device exhibits a JTOL corner-frequency of 50MHz and total jitter tolerance floor of 0.52 UI peak-to-peak @ BER of 10-10 in 28nm CMOS technology with 1.0V supply.