Taranjit Singh Kukal

IC-package co-design and analysis for 3D-IC designs

The implementation of a 3D IC is typically accomplished by multiple design teams, in multiple geographies, using a variety of design tools. Types of designs include a simple package, with an analog die and a digital die placed side-by-side and more complex designs include die stacks of multiple analog or digital dies in face-to-face configurations connecting with micro bumps. Through-silicon-vias (TSVs) provide an extra level of complexity allowing an individual die to connect to the component below and above it in the stack. Interposers (silicon or organic) provide greater functional density, performance, and reduced cost. Also used in 3D-IC design are package-in-package, and package-on-package design styles. This paper discusses five key ingredients necessary for the successful design of a 3D-IC regardless which method above is used. These five items are • Logical system-level integration to connect the system of ICs and packages, including support of layout-vs-schematic (LVS) checks • Physical co-design across IC and package boundaries through the sharing of component abstracts and cross-fabric functionality • Timing, power, and thermal-based design of the 3D-IC system in context of the package • Package-aware system simulation of 3D-IC circuitry • Management of physical and logical engineering change orders (ECOs)

Clock and data recovery module in 90nm for 10Gbps serial link with −18dB channel attenuation

A clock and data recovery (CDR) module in 90nm CMOS, for a 10Gbps serial link, integrated with a -18dB attenuation channel, is presented. A novel dual-loop CDR with separate charge pumps for high-gain frequency acquisition, and low-gain phase tracking has been introduced. The CDR utilizes a full rate architecture with a single VCO along with a selection logic for switching to the desired charge pump, resulting in a 4.2mW power consumption from the VCO. A current-steering charge pump with DCVSL inputs reduced the glitches in the up and down currents thereby reducing the ripples on the control voltage to 1mV in the locked condition. An rms and peak periodic jitter of 0.382ps and 0.759ps respectively were achieved with a PRBS sequence of 27 bits, resulting in a design compliant with SONET OC-192 specifications.

Tutorial T7B: RF Analysis and Simulation with Focus on RF SiP Methodology

Radio frequency (RF) involves complexities in the circuit design. Non-linearity issues in active as well as passive circuit designs and issues such as parasitic couplings and radiation effects introduce challenges in the RF circuit designs. Besides these, engineers face challenges, such as reduction in design cycle, overall development cost, and the time to market. To address these challenges, RF designs require extensive analysis and simulations techniques, as well as special measurement techniques. Traditionally, at the system level, separate groups design ICs and packages. However, cost, time-to-market issues, and ever-growing package complexity in the nanometer design space demand close collaboration between design groups. System level integration with SiP requires design flows and methodologies that bridge the gap between IC design and package design. An RF SiP is a complete functional system or sub system that includes multiple ICs from different or same process technology, and embedded passives connected using a complex RF structure. This system or sub system can either be packaged as an IC and mounted or integrated into a PCB. This tutorial will first introduce the basic understanding and challenges in RF system designs. This will be followed by the discussion on the analysis, simulation and measurement techniques used for RF designs. Finally, the tutorial would talk about the RF SiP flow and the design methodology. An RF SiP design example will be used to discuss various aspects of SiP, interfaces between IC layout and SiP layout, embedded components, interconnects, constraints, SiP level routing, design rule checks and RF SiP level simulation. In the next generation nanometer designs, the RF SiP design flow and methodology will be critical to meet the overall design requirements

Timing skew enabler induced by fiber weave effect in high speed HDMI channel by angle routing technique in 3DFEM

Fiber skew is one of the most difficult problems to debug. This paper investigates the timing skew problem on high speed, high-definition multimedia interface (HDMI) channel due to the fiber weave effect of Printed circuit board (PCB). This skew causes an asymmetry between the signals in the two lines and converts some of the differential signal into common signal, thereby, distorting the rise time of the differential signal, causing ISI, resulting in the collapse of the eye, and leading to deterministic jitter. In this paper, a method is proposed to minimize intra pair skew and jitter induced by the fiber weave effect. It is a geometry based method to understand the physical degradations in the PCB. The proposed method verified by using the 3DFEM technique in the differential line.

Modeling, design and automation of 5 Gbps serial link transceiver with jitter cancellation

In this paper, a generic high speed link transceiver is modeled, and this model is used to obtain high level design parameters for the design. With system level design inputs, the model is further developed to obtain optimum circuit level design parameters and other design level decisions for a given signal integrity specification. The model is developed using Algorithmic Modeling Interface (AMI), and design parameters for USB3.0 is obtained and USB3.0 transceiver is designed. The transceiver implemented in CMOS 90nm technology is discussed, and the results are compared with the models predicted results (thus validating the model). For USB3.0, a two tap FFE and a 3-tap DFE is found optimum and then circuit level design is implemented. This circuit-level implementation from the parameters obtained can be automated, thereby automating full design flow from specification to circuit. This automated flow to meet the given signal integrity specifications is discussed.