Tasuku Nishihara

Equivalence checking of high-level designs based on symbolic simulation

In this paper, we present a formal equivalence checking method for source-to-source refinements in C-based high-level hardware design descriptions. The method is based on word-level symbolic simulation, where variables and operators in designs are treated as uninterpreted symbols. In addition, we introduce a more efficient method utilizing the difference between two designs under verification. It can verify the equivalence faster when the similarity between the designs is large. We also show case studies of equivalence checking that were carried out with our verification framework FLEC.

A Post-Silicon Debug Support Using High-Level Design Description

In this paper, we propose a post-silicon debug framework utilizing high-level design description, which provides great advantage of comprehensibility and readability in analyzing erroneous behaviors for debugging complicated post-silicon errors. The framework consists of the following methods; mapping between high-level and RTL, extracting error-relevant portions, and rank them by the degree of relevance with the error. We also exhibit several experimental results to show its effectiveness.

Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis

Equivalence checking is one of the most important issues in VLSI designs to guarantee that bugs do not enter the design during optimization steps or synthesis steps. In this paper, we propose a new word-level equivalence checking method between two models before and after high-level synthesis or behavioral optimization. Our method converts two given designs into RTL models which have the same datapath so that the two designs have the same bit-level accuracy. Then the word-level equivalence checking techniques can be applied satisfying the bit-level accuracy. Also, as our method propagates equivalences from inputs to outputs with the equivalence rules of control structures, name correspondences among registers or variables are not required. By those rules, designs which have loops can be verified without unrolling. Experimental results with realistic examples show that our method can verify those designs in practical periods

Synthesis and formal verification of on-chip protocol transducers through decomposed specification

Protocol transducer which realizes translations between multiple protocols is one of the key components in IP-based design methodology. Although there have been researches on automatic synthesis of such protocol transducers, they cannot efficiently deal with out-of-order type communications frequently found in the state-of-the-art protocols. In this paper we present an automatic synthesis method which can deal with complicated state-of-the-art protocols by clearly separating control and datapath parts of the synthesized protocol transducers and introducing four types of configurations in the datapath parts of the protocol transducers. We also present a formal verification method based on inclusion checking between the given protocol transducer to be verified and the all possible protocol transducers which can be generated through our synthesis method. By using simulation-based filtering methods followed by a complete analysis of the entire design and state space, large and complicated protocol transducers can be efficiently and formally verified. Experimental results show their practical usefulness even for protocol transducers for complicated state-of-the-art protocols.

Slicing-based Hardware/Software Co-design Methodology From Functional Specifications

Program slicing is a software analysis technique and generates System Dependence Graphs (SDGs) by which dependences among program statements can be identified. In this paper, we propose a new hardware-software co-design methodology based on the static and partially dynamic dependence analysis with SDG. We start with any combinations of C, C++, and SpecC descriptions so that flexible functional specifications of the HW/SW systems can be made. First of all, the input descriptions are analyzed and verified with the SDG generated from the input descriptions. Actual analyses and verifications are based on static ones but partially with dynamic ones as well, and fairly large descriptions can be processed. After these analyses, we divide the system into hardware and software parts by optimizing the design descriptions and introducing parallelism if necessary. In this HW/SW partitioning, SDG generated from C / C++ / SpecC design descriptions is fully utilized to extract / convert / pack the HW parts from the entire descriptions. This flexibility of HW/SW partitioning is one of the main differences from previous HW/SW partitioning methods. The extracted HW parts are further optimized and then converted into RTL descriptions by existing behavioral synthesis tools. As the last step, the generated RTL descriptions together with SW parts are compared to the original descriptions in order to make sure that they are logically equivalent. Also, designer-specified properties may be model checked with these final design descriptions. These equivalence checking and model checking can be realized by first translating the HW/SW design descriptions into FSM type representations. The translated FSM type representations are further processed by existing formal verifiers. We present the proposed HW/SW co-design methodology with an illustrating example as well as actual application to real designs and demonstrate the usefulness of our approach.

Development and Verification of a Collaborative Printing Environment

In this paper, we propose a printing environment utilizing collaboration to offer more reliable printing environment. In the proposed environment, printers are clustered, and collaborative printing is carried out among clusters if one cluster is very busy and others are not. We also work on the formal verification problem of such collaborative environment, since a number of properties must be satisfied in the environment to guarantee the secure and safe printing. To prove such properties, we apply model checking methods to the developed environment. We have developed a simulator of the proposed environment, and show that it can work effectively even if some printers are out of order, or out of paper. Also, applying model checking, we successfully prove the properties that must be satisfied in such printing environments.

System LSI distributed collaborative design environment for both designers and CAD developers/engineers

In this paper we propose a distributed system LSI design environment where both LSI designers and CAD tool developers/engineering can collaboratively work for higher performance designs. What we propose is a framework where not only design issues but also CAD tool related problems can be simultaneously taken care of by both designers and CAD engineers. Traditional design tools and flows are assuming to use CAD tools which have been fully developed and cannot be modified or enhanced when designing LSI chips. In order to use the most advanced LSI technology, however, it is essential to use the most advanced CAD tools which may not be fully debugged and tuned yet. This means that CAD tools must be enhanced when designing a new advanced LSI chip. Also we briefly discuss about implementation issues of the proposal on top of Croquet type distributed environments by showing a debugging process of hardware logic designs. We define consistency conditions on the use of CAD tools for the target LSI design flows including interface issues among various CAD tools used in the design flow and analyze them with a method similar to model checking type approaches used in formal analysis. We define virtual shared screens for both LSI designers and CAD developers/engineers collaboration and monitors activities on them, which are the base of our model checking type analysis. We examine various issues including interface checking among CAD tools, interface checking among design blocks, and tool performance enhancement/design modifications

Performance Estimation with Automatic False-Path Detection for System-Level Designs

When designing todays highly complicated systems consisting of several hardware and software modules, it is essential to estimate the performance such as worst-case or best-case execution time in early design stages. Such estimation is essential to explore architecture and hardware/software partitioning in system-level design. A maximum execution time estimated topologically without considering false-paths is longer than the real. In this paper, we propose an static estimation method of maximum execution time in system-level designs, considering false-paths. Also, we adopt an approximation approach in order to avoid the path explosion problem. The experimental results show that our method can provide much smaller estimated maximum execution time than the method without considering false-paths. At the same time, the results show us that the maximum execution time can be estimated to a very small range, by applying both simulation-based method and our static method.

Multi-level Bounded Model Checking to detect bugs beyond the bound

Bounded Model Checking is a widely used technique both in hardware and software verification. However, it cannot be applied if the bounds (number of time frames to be analyzed) becomes large. Therefore it cannot detect bugs that can be observed only through very long sequence counter-examples. In this paper, we present a method connecting multiple BMCs by sophisticated uses of inductive approach and symbolic simulation. The proposed method can check unbounded properties by analyzing loop behaviors in the design with decision procedures. In our verification flow, a property is automatically decomposed and refined instead of designs. First, a property is decomposed not to consider the reachability from the initial states of the design. Next, if a counter-example is found, the condition to enter it is generated by symbolic simulation. Finally, the reachability from the initial states to the states where the condition becomes true is checked inductively by another Bounded Model Checking. If they are not reachable from the initial states, then the property is refined not to enter the unreal counter-example. Key observation here is that each BMC does not need to process so many time frames as compared with pure BMC from initial states. Therefore, the proposed method can process much larger bounds. Experimental results with two examples have confirmed this advantage.