Tatsuo Morita

Suppression of current collapse by hole injection from drain in a normally-off GaN-based hybrid-drain-embedded gate injection transistor

Current collapse is suppressed up to 800u2009V of drain voltage in our proposed device, Hybrid-Drain-embedded Gate Injection Transistor (HD-GIT), where an additional p-GaN layer is grown on the AlGaN barrier layer and is connected to the drain electrode. We present, based on a device simulation and electroluminescence study, that the hole injection from the additional drain-side p-GaN at the OFF state compensates the hole emission in the epilayer. As a result, the gate-drain access region is not negatively charged at the OFF state, resulting in the drastic suppression of current collapse in HD-GIT.

Interface disorder in GaAs/AlGaAs quantum wells grown by molecular beam epitaxy on 0.5°‐misoriented (111)B substrates

The interface disorder in quantum wells (QW’s) grown by molecular beam epitaxy on 0.5°‐misoriented (111)B GaAs substrates was characterized by low‐temperature photoluminescence and by transmission electron microscopy. It was found that the abruptness of the heterointerface of (111)B QW’s is as sharp as that of (100) QW’s. The effect of growth interruption at a high substrate temperature of 720u2009°C on the interface disorder was also studied and was found to be detrimental.

In Situ Ellipsometric Monitoring of the Growth of Polycrystalline Silicon Thin Films by RF Plasma Chemical Vapor Deposition.

Polycrystalline silicon thin films have been deposited by RF plasma-enhanced chemical vapor deposition (CVD) using SiF4, SiH4 and H2 gases at a substrate temperature of 300° C. Growth of the films has been monitored by spectroscopic ellipsometry, and time resolved film compositions have been investigated. The film deposited with SiH4 diluted by H2 at a power level of 500 mW/cm2 showed crystal fraction of 50%, and it increased up to 80% with addition of SiF4, although the deposition rate decreased and the surface roughness was enhanced. These results suggest that preferential etching of amorphous tissue brings about the increase of crystalline fraction. Crystallization of the film was verified by transmission electron microscopy along with the decrease in hydrogen content shown by the infrared absorption spectrum.

Facile Carbon Fixation to Performic Acids by Water-Sealed Dielectric Barrier Discharge

Carbon fixation refers to the conversion of carbon dioxide (CO2) to organic materials, as commonly performed in nature through photosynthesis by plants and other autotrophic organisms. The creation of artificial carbon fixation processes is one of the greatest challenges for chemistry to solve the critical environmental issue concerning the reduction of CO2 emissions. We have developed an electricity-driven facile CO2 fixation process that yields performic acid, HCO2OH, from CO2 and water at neutral pH by dielectric barrier discharge with an input electric power conversion efficiency of currently 0.2−0.4%. This method offers a promising future technology for artificial carbon fixation on its own, and may also be scaled up in combination with e.g., the post-combustion CO2 capture and storage technology.

Crystallization Phenomenon Induced by Proton Beam Irradiation using Large Area Ion Implantation for Polycrystalline Silicon Thin Film Transistors

Crystallization induced by proton beam irradiation using large area ion implantation at low temperature (less than 600°C) have been investigated. Phosphine gas containing hydrogen of more than 95% is discharged by RF power of 100W. Both phosphorus ions and protons are accelerated by a potential of 100kV and implanted into polycrystalline silicon (poly-Si) layers. At a range of beyond 2×10 15 ions/cm 2 P 1 ions dose, amorphous phase is primarily formed and then changes into polycrystals again and its grain sizes grow up to 50nm in average diameter. The crystallization is found to occur simultaneously with phosphorus doping and to depend on the amount of the irradiated protons. This technique enables us to eliminate the activation annealing process for implanted dopant.

Dislocations in In0.1Ga0.9As/GaAs multilayers epitaxially grown on Si substrates

Dislocations in In0.1Ga0.9As/GaAs multilayers grown on Si substrates have been examined by using transmission electron microscopy. It is found that two types of misfit dislocations exist at the interfaces of multilayers which are composed of layers thicker than the critical thickness (hc). One is a 60° dislocation and the other is a pure edge dislocation. It is considered that a 60° dislocation can glide to adjacent layers from the interface, while a pure edge dislocation can also go out of the interface. The stress field caused by closely located dislocations introduces bowing of dislocation lines followed by cross slipping.

Mechanism of Current-Collapse-Free Operation in E-Mode GaN Gate Injection Transistors Employed for Efficient Power Conversion

Due to the superior characteristics of GaN to Si, they can be utilized to drastically increase the efficiency and minimize the size of power converter system. However, there has been a critical issue of the so-called current collapse where ON-state resistance is increased once GaN transistor is exposed to high voltage. From the temperature dependence of the switching characteristics of an enhancement-mode GaN transistor, we found that deep ``hole traps play an important role in the current collapse. Based on this finding, we proposed a new device structure where hole emission in the OFF state is compensated by the holes injected from a drain-side pGaN. It was found that the proposed device is free from current collapse up to 800V. In this paper, we proposed the mechanism for the suppression of the current collapse in the proposed GaN transistor.

Fully-Selfaligned Al Gate Polysilicon TFT LCD Driver Circuits

The performance of scanning driver circuits fabricated with low temperature self-aligned Al gate polysilicon TFTs is demonstrated. After the gate electrode patterning, the fabrication process temperature is kept below 400C to enable the use of alu minum gate electrodes. The lo w temp erature crys tallization phenomeno n, which oc curs when protons are implanted simultaneou sly with boron or phosphorus dopants, is employed to eliminate the 600oC activation annealing process. A maximum clock frequency of about 2.OMH z is achieved when the driver operating voltage is 24V and the TFT channel length is t21tm.

Effect of Drain Conductance in Equivalent Circuit Model for GaN GIT Bidirectional Switch

GaN-Gate Injection Transistor (GIT) 双方向スイッチは 2 つのゲート電極からチャネル電流を 制御でき、GaN トランジスタ回路の素子数低減,規模縮小などが期待できる [1]。我々はこの 素子を用いたスイッチング回路を設計するための等価回路モデルを提唱してきた [2]。今回は、 GaN-GIT 双方向スイッチの等価回路モデルにドレインコンダクタンスの影響を考慮すること で、従来よりも実験波形に対して高精度に一致させることができたので報告する。 GIT 双方向スイッチの等価回路モデルは従来通り 1 つの電流源(Ich)と 3 つの容量(CG1S1, CR, CD)で構成され、容量パラメータはスイッチング波形から見積る手法により抽出した [2]。電 流源 Ich はこれまでパルス I-V 測定で求めていたが、今回はそのパラメータにドレインコンダ クタンス gdの効果を加えた。この gdにより、図 1 の IS2S1-VS2S1特性には VS2S1に比例して IS2S1 が上昇する特性が加わっている。gd は容量パラメータと同じスイッチング波形から求めてお り、図 2 中の区間 I で示された領域での IS2S1一定のときの VG1S1と VS2S1の関係から見積った。 図 3 はチョッパー回路におけるスイッチング波形の実験値と計算値を比較したものである。 ゲート抵抗は RG1 = 177Ωとした。図 3(a)はドレインコンダクタンスを加えていないもの、(b) は加えているものである。図 3(a)では IS2S1が上昇を終えると区間 I では VG1S1の計算波形が一 定値となっており、VS2S1 の計算波形は実験波形と比べて早く減少している。一方、図 5(b)で はドレインコンダクタンスの効果によって区間 I において VG1S1の計算波形は実験波形によく 一致し、さらに VS2S1波形の計算精度も向上した。参考文献 [1] T. Morita et al., Dig. IEEE Int. Electron Device Meeting, Washington, USA, 2007, 865. [2] T. Ide et al., IEEE Trans. Electron Devices, 59, 2643, 2012.謝辞 本研究の一部は NEDO 戦略的省エネルギー技術革新プログラムの援助に より行われた。

Structural Investigations of Polycrystalline Silicon Films Prepared by Plasma Enhanced CVD

Among several growth techniques_ of a pollcrlstalline silico-n f ilm, pl.asna enhanced ihernical vapour deposition(PECVD) followed by solid phase Srowth is one of useful netliods in appl icat ions for giant micro-electronics for inOustrial use, because of the-Low-tenperature process below 600C. From an electrical point of view, both the polycrystallinq Srain-s_ize including its quality andthe nature of_ grain boundaries including itg den-sity govern the iharacieristics of a thin filrn transistor. l{e investigated their dependence on deposition conditions and on subsequent proc,esses in full detail. This is the f iist report on a f abricat ing condi t ion and an analyt ica.l -resul t of devi cequliity iolycrystalline silicon films usins PECVD process belo-w 500t. fhi-s paper f ocuses on the bas ic charact erizat ion of a f i lm_ grow-n by an above PECVD riethod under various conditions in terms of structural analysis by Ranan scattering and TEII, showing the effective size of a grain and the stress in a filn. Growth temperature dependence of defect density was also observed by an electron spin resonance(ESR).