Taufiq Alif Kurniawan

A 2.5-GHz band low-voltage class-E power amplifier IC for short-range wireless communications in 180-nm CMOS

A fully integrated class-E power amplifier IC in 180-nm CMOS is presented for 2.5-GHz band short range wireless communication systems. To realize high efficiency with low operation voltage, a class-E amplifier with back gate effect has been designed, fabricated and fully evaluated. The proposed amplifier IC can operate at a supply voltage from 0.5 V to 1.5 V. The amplifier IC exhibits a P1dB of 6.9 dBm and a saturated output power of 10.7 dBm with a maximum drain efficiency of 36.4% at a 1.0 V power supply.

A 2.5-GHz band, 0.75-V high efficiency CMOS power amplifier IC with third harmonic termination technique in 0.18-µm CMOS

In this paper, a 2.5-GHz band fully integrated high efficiency CMOS power amplifier IC with third harmonic termination technique for low supply voltage was designed, fabricated and fully evaluated in 0.18-μm CMOS technology. Since the proposed third harmonic termination technique effectively increases the PAE by reducing the rms drain current, the total dc power consumption is diminished. To control a threshold voltage for low supply voltage application, a 0.5-V back-gate voltage is applied for the transistor. The power amplifier IC exhibits an output power of 8.5 dBm and a peak PAE of 31.1 % at a supply voltage of only 0.75-V.

Highly linear high isolation SPDT switch IC with back-gate effect and floating body technique in 180-nm CMOS

This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Back-gate voltage injection and floating body technique are utilized to improve the power handling capability, insertion loss and isolation performance, simultaneously. The fabricated SPDT switch IC has exhibited an input referred 0.3-dB compression point of 21.0 dBm, an isolation of 42.7 dB and an insertion loss of 1.1 dB for transmit mode at an operation frequency of 5.0 GHz.

Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS

This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Floating body technique and stacked nMOSFETs are utilized to improve the power handling capability and isolation performance. The fabricated SPDT switch IC has exhibited an input referred 0.5-dB compression point of 21.8 dBm, an isolation of 42.4 dB and an insertion loss of 1.2 dB for transmit mode at an operation frequency of 5.0 GHz. The SPDT switch IC has an insertion loss of 2.1 dB and a return loss of 10.6 dB for receive mode at 5.0 GHz.

A 2.5-GHz band low-voltage high efficiency class-E power amplifier IC with body effect

This paper presents a fully integrated class-E power amplifier IC with body effect to achieve high efficiency and high gain at low supply voltage for 2.5-GHz band short range wireless communication systems. The class-E amplifier IC is designed, fabricated and fully evaluated in 180-nm CMOS. The proposed power amplifier IC exhibits a small-signal gain of 10.8 dB and a saturated output power of 10.8 dBm with a drain efficiency of 35.0 % at a supply voltage of only 1-V.

Design of Quad-Band Bandpass Filter Lumped-Element Using Shunt Resonator and Independent Transmission Zero

The return loss and VSWR of the fabricated quadband BPF are satisfied to the design specifications.

Design of Power amplifier for Radio-Frequency Identification application on 13.56 MHz

Radio-Frequency Identification (RFID) has become a technology segment that growth rapidly in data collecting industry and automatic identification. One of the most important part of RFID system is power amplifier that enable power transfer between reader and transponder for identification purpose. This research is proposed power amplifier class E for RFID application at frequency of 13.56 MHz. It is shown from the results that the proposed power amplifier had a very good performances on return loss both on input and output, gain, stability, and efficiency.

Design of concurrent multiband inductive degeneration low noise amplifier with LC resonator

In this research, the concurrent multiband LNA that works at four frequency centers of 950 MHz, 1.85 GHz, 2.35 GHz, and 2.65 GHz will be designed and analyzed. The multiband LNA uses transistor HJ-FET NE3210S01 in cascode structure with self bias and inductive degeneration topology with resonator LC. The performances of multiband LNA are simulated by Advance Design System (ADS). It is shown from the simulation results that, at four frequency centers of 950 MHz, 1.85 GHz, 2.35 GHz, and 2.65 GHz, the S21 achieves 21.77 dB, 17.88 dB, 16.71 dB, and 15.85 dB respectively, the S11 achieves -23.23 dB, -20.46 dB, -17.93 dB, and -19.69 dB respectively, the NF achieves 0.73 dB, 0.69 dB, 0.68 dB and 0.75 dB respectively.