Te-Kuang Chiang

A Quasi-Two-Dimensional Threshold Voltage Model for Short-Channel Junctionless Double-Gate MOSFETs

Based on the bulk conduction mode of the quasi-2-D scaling theory, an analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation. The model can also be extended to modeling accumulation/inversion operation mode for JL/junction-based double-gate MOSFETs. The model is verified by 2-D device simulations and can be easily used to explore the threshold voltage behavior of the JL double-gate MOSFETs due to its simple formula and computational efficiency.

A New Quasi-2-D Threshold Voltage Model for Short-Channel Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs

Based on the quasi-2-D scaling equation, a new threshold voltage model for short-channel junctionless (JL) cylindrical surrounding gate (JLCSG) MOSFETs is developed. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage behavior. The model can also be extendable to its counterpart of junction-based cylindrical surrounding gate (JBCSG) MOSFETs. The model is verified by its calculated results matching well with those of the 3-D numerical simulator and can be easily used to explore the threshold voltage characteristics of JLCSG MOSFETs for its simple formula and computational efficiency.

A Compact Model for Threshold Voltage of Surrounding-Gate MOSFETs With Localized Interface Trapped Charges

Based on the perimeter-weighted-sum method and scaling theory, a compact threshold voltage model for surrounding-gate MOSFETs with localized interface trapped charges is developed by considering the effects of equivalent oxide charges on the flat-band voltage. The model shows how various charge conditions such as the positive/negative trapped charges and device structure parameters such as the silicon thickness, oxide thickness, and channel length affect the threshold voltage behavior. The model is verified by the 3-D device simulator and can be efficiently used to explore hot-carrier-induced threshold voltage degradation of the charge-trapped memory device.

A new two-dimensional analytical subthreshold behavior model for short-channel tri-material gate-stack SOI MOSFET's.

Abstract On the basis of the exact solution of the two-dimensional Poisson equation, a new analytical subthreshold behavior model consisting of the two-dimensional potential, threshold voltage, and subthreshold current for the short-channel tri-material gate-stack SOI MOSFET’s is developed. The model is verified by its good agreement with the numerical simulation of the device simulator MEDICI. The model not only offers physical insight into the device physics but also provides guidance for the basic design of the device.

A New Two-Dimensional Analytical Threshold Voltage Model for Short-Channel Triple-Material Surrounding-Gate Metal--Oxide--Semiconductor Field-Effect Transistors

A new analytical model for the surface potential and threshold voltage of triple-material surrounding-gate (TM-SGT) metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed to investigate short-channel effects (SCEs). The TM-SGT MOSFET forms a two-step potential in the channel and effectively reduces the SCEs and the variation of threshold voltage compared with those of dual-material surrounding-gate (DM-SGT) and triple-material double-gate (TM-DG) MOSFETs. TM-SGT MOSFETs thus have better performance than DM-SGT and TM-DG MOSFETs.

A Novel Quasi-3-D Threshold Voltage Model for Fully Depleted Quadruple-Gate (FDQG) MOSFETs: With Equivalent Number of Gates (ENG) Included

Instead of solving the three-dimensional (3-D) Poissons equation, we present a novel quasi-3-D threshold voltage model for fully depleted quadruple-gate (QG) MOSFETs based on the minimum central potential derived from the quasi-3-D scaling equation. Accounting for short-channel effects (SCEs) on the device, the natural length of the QG FET in the scaling equation is obtained from the equivalent number of gate equation of 1/ λ_QG² = 1/ λ_DG1²+1/ λ_DG2², where the QG device working in x-y-z space with natural length of λ_QG can be broken into two equivalent double-gate (DG) FETs with natural lengths of λ_DG1 and λ_DG2 working in y-z and x-z planes, respectively. Numerical simulation data for threshold voltage roll-off and drain-induced barrier lowering effects (DIBL) were compared to the model to validate the formula. Among QG FETs with the same perimeters, one with a square cross section will show the worst immunity to SCEs due to the largest natural length. With the criterion of DIBL≤50 mV, an improvement of up to 30% is illustrated in the minimum channel length for the QG MOSFET in comparison to the DG MOSFET.

A Novel Scaling Theory for Fully Depleted, Multiple-Gate MOSFET, Including Effective Number of Gates (ENGs)

This brief presents a novel scaling theory for fully depleted, multiple-gate (MG) MOSFET. The scaling theory is derived from the equation for effective number of gates (ENGs), ENG_QG=ENG_DG,1+ENG_DG,2 where the MG device can be genuinely broken into two equivalent double-gate (DG) transistors working in parallel based on the perimeter-weighted-sum method. Numerical device simulation data for drain-induced-barrier-lowering were compared with the model to validate the formula. Using the scaling theory, the minimum effective channel length improvement factor of ρ_MG=1-(ENG_DG/ENG_MG)^1/2 shows an improvement of up to 30% in the minimum effective channel length for the MG MOSFET in comparison with DG MOSFET.

A novel scaling-parameter-dependent subthreshold swing model for double-gate (DG) SOI MOSFETs: including effective conducting path effect (ECPE)

We have developed a novel scaling-parameter-dependent subthreshold swing model. By considering the effective conducting path effect (ECPE), this model generalizes the previous subthreshold swing model and precisely predicts the subthreshold swing for DG SOI MOSFETs without considering quantum effects. The model shows that the subthreshold swing could depend only on a scaling device parameter (α3). The calculated subthreshold swing S matches well with the simulated results by MEDICI. Our model is simple and offers an efficient scaling rule for DG SOI MOSFETs.

A new two-dimensional subthreshold behavior model for the short-channel asymmetrical dual-material double-gate (ADMDG) MOSFET’s

Abstract Based on the exact solution of two-dimensional Poisson’s equation, a novel subthreshold behavior model comprising channel potential, subthreshold swing, and threshold voltage for the short-channel asymmetrical dual-material double-gate (ADMDG) MOSFET’s have been developed. The model is verified by its simulation results that agree well with those of the two-dimensional numerical simulator. Besides offering the physical insight into device physics, the model provides the basic designing guidance for the ADMDG MOSFET’s.

A compact, analytical two-dimensional threshold voltage model for cylindrical, fully-depleted, surrounding-gate (SG) MOSFETs

Based on two-dimensional(2D) potential analysis, a compact, analytical model for threshold voltage in cylindrical, fully-depleted, surrounding-gate(SG) MOSFETs is derived. The minimum surface potential μmin,surfaceis used to develop the threshold voltage model. Besides decreasing the characteristic factor, both the thin silicon body and gate oxide can reduce the threshold voltage roll-off simultaneously. It is also found that the threshold voltage shift is dependent on the scaling factor of λ1L. The high scaling factor is preferred to alleviate threshold voltage degradation.