Teck Kheng Lee

A novel joint-in-via flip-chip chip-scale package

It is believed that the slower-than-expected adoption of flip-chip (FC) packages is due to the lagging advancement in substrate designs and technologies with front-end processes. This lag has also resulted in the need for a costly redistribution layer (RDL), which fans out the die pads to meet the substrate design rule. This paper reviews the photographic metallization limitation of organic substrates and proposes an innovative joint-in-via architecture using existing substrate technologies to improve the pad pitch resolutions. The joint-in-via architecture consolidates the landing pads, the micro-vias, and the flip-chip joint into one common element, thereby saving valuable substrate real estate for high-density routing. It has been successfully conceptualized on a flex laminate at a pad pitch of 70 /spl mu/m and a receiving pad size of 50 /spl mu/m, potentially enabling the removal of the RDL layer for packaging. Robustness in flip-chip assembly is improved by the joint-in-via architecture because it prevents solder bridging and allows the use of existing packaging infrastructure. A new flip-chip, chip-scale package (FC-CSP) has evolved with the implementation of the joint-in-via architecture. With material optimization, the FC-CSP passes standard reliability tests, further demonstrating the robustness of the joint-in-via technology.

Instantaneous fluxless bonding of Au with Pb–Sn solder in ambient atmosphere

A fluxless bonding technique has been developed as a method of flip-chip bonding for microelectronic packaging. The fluxless bonding technique can be achieved instantaneously in an ambient environment between metallic stud bumps and predefined molten solder. This paper describes the mechanics of the bonding action and verifies the effectiveness of this bonding method through wetting balance tests and scanning electron microscope and energy dispersive x-ray analysis. This technique has been demonstrated by using a gold stud bump to break the tin oxide layer over molten solder. This allows for a fast, solid liquid interdiffusion between gold (Au) and the fresh molten eutectic lead-tin (Pb–Sn) solder for joint formation during solidification. This bonding method has been successfully tested with 130-μm-pitch flip-chip bond pads on a joint-in-via flex substrate architecture.

Fine Pitch Au-SnAgCu Joint-in-via Flip-Chip Packaging

One of the obstacles for wide adoption of flip chip in semiconductor packaging lies in the geometry pitch mismatch between die and substrate. This is due to the lagging advancement in substrate designs meant to satisfy the corresponding pad pitch on the die. This paper introduces an innovative joint-in-via (JIV) architecture to improve pad pitch resolutions on substrates. Different micro-via formation techniques (mechanical punch, chemical etch and laser) are assessed on both rigid and flexible substrate to realize the JIV architecture. A 70 mum-pitch substrates with a landing pad size of 50 mum has been successfully implemented for direct flip- chip application. At a larger pad pitch, the JIV offers a large receiving pad size and enables the use of conventional die bonders for flip-chip bonding. A solid-liquid interdiffusion bonding technique, using compressive force (SLICF), was chosen with the Au-SnAgCu solder system to achieve an instantaneous fluxless, lead-free, flip-chip bonding. Intermetallic analyses were identified using Scanning Electron Microscope and Energy-dispersive X-ray analysis to study the Au-SnAgCu system. Preliminary package assessment showed that the JIV using Au-SnAgCu is able to pass the standard reliability tests.

Prototyping of low-cost wafer level packages

WLP with various design configurations is fast becoming a common package for high performance applications. Besides large-die or embedded WLPs in System-in-Package, technology development in the industry also focuses on cost-effective WLP with acceptable level of functional and reliability performances, suitable for low-pin-count or small-die applications. Nepes is developing a series of low-cost wafer level packages (LCWLPs) to address the cost and technology demands. This paper will focus on prototyping of a non-UBM LCWLP with RDL, to be used as a baseline for relative cost, functional and reliability performances comparison with conventional WLPs and future LCWLPs of the same die sizes and ball layout. Previously, simulations were performed to confirm good electrical, mechanical (warpage and thermal cycling) and thermal performances of LCWLP. Here, process development is carried out to fabricate prototype of LCWLP. Several process issues are successfully resolved. Subsequently, LCWLP is qualified under package level reliability tests, including multi-reflow, solder shear/pull tests, pressure cooker test (PCT), and high temperature storage (HTS) test. After package level qualification, effort will be spent on board level tests. Here, board level drop test simulations are conducted for 3 different sizes of LCWLP. They are shown to have reasonable drop test performance, comparable to typical BGAs.

A novel joint-in-via, flip-chip chip-scale package

It is believed that the slower-than-expected adoption of flip-chip (FC) packages is due to the lagging advancement in substrate designs and technologies with front-end processes. This lag has also resulted in the need for a costly redistribution layer (RDL), which fans out the die pads to meet the substrate design rule. This paper reviews the photographic metallization limitation of organic substrates and proposes an innovative joint-in-via architecture using existing substrate technologies to improve the pad pitch resolutions. The joint-in-via architecture consolidates the landing pads, the micro-vias, and the flip-chip joint into one common element, thereby saving valuable substrate real estate for high-density routing. It has been successfully conceptualized on a flex laminate at a pad pitch of 70 /spl mu/m and a receiving pad size of 50 /spl mu/m, potentially enabling the removal of the RDL layer for packaging. Robustness in flip-chip assembly is improved by the joint-in-via architecture because it prevents solder bridging and allows the use of existing packaging infrastructure. A new flip-chip, chip-scale package (FC-CSP) has evolved with the implementation of the joint-in-via architecture. With material optimization, the FC-CSP passes standard reliability tests, further demonstrating the robustness of the joint-in-via technology.

Assessment of Fluxless Solid Liquid Interdiffusion Bonding by Compressive Force of Au-PbSn and Au-SAC for Flip Chip Packaging

Flip chip packaging faces two primary bonding-process obstacles: flux use and geometry mismatch between die and substrate pad pitch. These obstacles motivated the development of a fluxless bonding method called solid-liquid interdiffusion bonding by compressive force (SLICF). SLICF utilizes a mechanical force to form the bond through solid-liquid interdiffusion with a joint-in-via (JIV) architecture for flip chip packaging. SLICF bonding (also known as Thermo-mechanical (TM) bonding) forms an instantaneous bond and eliminates the need for reflow infrastructure. Both Au-PbSn and Au-SAC interconnect systems were studied for the SLICF bonding on the JIV architecture at a 130 mum pitch. The morphologies of Au-PbSn and Au-SAC in solid-liquid interdiffusion were studied with their kinetics measured by the Au consumption rate. The SLIFC bonds for Au-PbSn and Au-SAC were compared and assessed by mechanical shear tests and thermomechanical stresses. Au with PbSn was found to perform marginally better due to its joint geometry and slower kinetics.

Interfacial Adhesion Studies using Double Cantilever Beam Method and Shear Testing

The interfacial adhesion between two packaging materials is important to package reliability performance. This paper compares the interfacial characterization technique of hot and standard die shear tests versus the double cantilever beam (DCB) method. The study involved the interfacial adhesion of die attach material to the soldermask, the core surface of an organic substrate, and the silicon die surface. Both room temperature and heated shear tests showed a cohesive failure mode and thus presented difficulties in quantifying the interface adhesion between materials interfaces. The DCB tests resulted in a reproducible adhesive failure under mode 1 condition for the tested interfaces. The computed energy release rate Gc quantified the adhesion between the different interfaces. The package reliability of the different interfaces was assessed in FBGA packages with their failure modes correlated to the adhesion strength and failure modes of the DCB test. The DCB test is recommended as a material selection tool, to be used in conjunction with shear tests for materials or surface selection.

Dynamic Testing of Solder Joint Strength under Compression, Tension and Shearing

Studies on strain rate sensitivity of solder joints at high rates are relatively scarce. This investigation explores the possibility of establishing an experimental technique using a split Hopkinson bar to test single solder specimens. Computational simulation of tests on a cylindrical specimen the size of the solder ball is also performed to validate the assumption of one dimensional wave propagation as well as accuracy of stress-strain data derived. Tests on actual 0.24 mm diameter solder balls show good repeatability of results, confirming the feasibility of applying the SHB technique. Average dynamic stress-strain curves for strain rates ranging from 102/s to 103/s were obtained and compared with average responses corresponding to quasi-static strain rates of 10-3 /s and 1/s for compression, tension and shear loading. Rate sensitivity of the solder ball response is observed.

Interface Reactions and Shear Strength of Lead-Free Sn-3.5Ag Solder with Ni-W-P Metallization

Conventional electroless Ni-P metallizations have been found to be inadequate for providing long term protection of the underlying metallization due to their P content, which leads to complicated interfacial reactions. The use of lead-free solder accelerates interfacial reaction because its Sn content is higher than that in conventional Pb-Sn solders. It is believed that codeposition of W into the Ni-P can effectively retard Ni-P precipitation and Ni crystallization, and thus enhance the solder joint reliability. In this study, the microstructure and shear joint strength of electrolytic Ni, electroless Ni-P and electroless Ni-W-P metallizations were investigated. All 3 metallizations were subjected to reflow soldering followed by thermal aging, and finally ball shear tests. It was found that electrolytic Ni and electroless Ni-W-P behave similarly in terms of IMC thickening rates and ball shear strength, and both have outperformed Ni-P.

Effects of Sterilization Cycles on PEEK for Medical Device Application

The effects of the sterilization process have been studied on medical grade thermoplastic polyetheretherketone (PEEK). For a reusable medical device, material reliability is an important parameter to decide its lifetime, as it will be subjected to the continuous steam sterilization process. A spring nature, clip component was selected out of a newly designed medical device (patented) to perform this reliability study. This clip component was sterilized for a predetermined number of cycles (2, 4, 6, 8, 10, 20…100) at 121 °C for 30 min. A significant decrease of ~20% in the compression force of the spring was observed after 30 cycles, and a ~6% decrease in the lateral dimension of the clip was observed after 50 cycles. No further significant change in the compression force or dimension was observed for the subsequent sterilization cycles. Vickers hardness and differential scanning calorimetry (DSC) techniques were used to characterize the effects of sterilization. DSC results exhibited no significant change in the degree of cure and melting behavior of PEEK before and after the sterilization. Hardness measurement exhibited an increase of ~49% in hardness after just 20 cycles. When an unsterilized sample was heated for repetitive cycles without the presence of moisture (121 °C, 10 and 20 cycles), only ~7% of the maximum change in hardness was observed.