Ted Thorbeck

Formation of strain-induced quantum dots in gated semiconductor nanostructures

A long-standing mystery in the field of semiconductor quantum dots (QDs) is: Why are there so many unintentional dots (also known as disorder dots) which are neither expected nor controllable. It is typically assumed that these unintentional dots are due to charged defects, however the frequency and predictability of the location of the unintentional QDs suggests there might be additional mechanisms causing the unintentional QDs besides charged defects. We show that the typical strains in a semiconductor nanostructure from metal gates are large enough to create strain-induced quantum dots. We simulate a commonly used QD device architecture, metal gates on bulk silicon, and show the formation of strain-induced QDs. The strain-induced QD can be eliminated by replacing the metal gates with poly-silicon gates. Thus strain can be as important as electrostatics to QD device operation operation.

Determining the location and cause of unintentional quantum dots in a nanowire

We determine the locations of unintentional quantum dots (U-QDs) in a silicon nanowire with a precision of a few nanometers by comparing the capacitances to multiple gates with a capacitance simulation. Given that we observe U-QDs in the same location of the wire in multiple devices, their cause is likely to be an unintended consequence of the fabrication, rather than of random atomic-scale defects as is typically assumed. The locations of the U-QDs appear to be consistent with conduction band modulation from strain from the oxide and the gates. This allows us to suggest methods to reduce the frequency of U-QDs.

Location and cause of surface potential fluctuations in an SOI nanowire

Moving to a three dimensional architecture, such as finFETs (field effect transistor), tri-gate FETS or nanowires, will allow semiconductor devices to scale for a few more nodes. Using the third dimension, these devices offer the same surface area but take up less space on the wafer, at the cost of a possible increase in sensitivity to non-idealities. Smaller devices are likely to be more sensitive to random charged defects. A 3D channel has an increased potential for local strains due to the oxide and the gates compared to a 2D device. Since both charged defects and strain change the surface potential in the channel, these effects could change the threshold voltage. Additionally, local changes in the stress cause local changes in the mobility of the channel. So to improve device uniformity, a technique to determine the possible causes of a surface potential fluctuation would be useful.