Teemu Pitkänen

Low-power, high-performance TTA processor for 1024-point fast fourier transform

Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.

Fixed- and Floating-Point Processor Comparison for MIMO-OFDM Detector

The evolution toward software-defined radio (SDR) technologies, in particular, cognitive radios, is leading toward the need to support multiple radio solutions with the same baseband processing resources. This implies not only a huge design effort, but also a shift from hardware to software design flavored tool chains. In this paper, a hardware complexity and energy dissipation are analyzed by implementing three programmable processor architectures that support 32- and 12-bit floating-point and 16-bit fixed-point arithmetics. The processors are based on the transport triggered architecture (TTA) that has a very low programmability overhead. We programmed a recently introduced selective spanning with fast enumeration (SSFE) soft-output detector for these processors. The processors are capable to achieve data rates required in multiple-input multiple-output orthogonal frequency- division multiplexing (MIMO-OFDM) 3G LTE system with a small energy dissipation. The analysis shows that at the same goodput rate a floating-point implementation can achieve a lower gate count and a better power efficiency than a fixed-point design. Combined with tool chain benefits, the floating-point arithmetic is becoming attractive for future SDR solutions.

Hardware cost estimation for application-specific processor design

In this paper, a methodology for estimating area, energy consumption and execution time of an application executed on a specified processor is proposed. In addition, a design exploration process to find suitable processor architectures for a specific application is proposed. Cost and performance estimation is an important part of the exploration process. The actual cost estimation is based on predefined characterizations of cost and performance of resources stored in a database. The results show that the method is quick and its accuracy is sufficient for design space exploration.

Low-Power Application-Specific Processor for FFT Computations

In this paper, a processor architecture tailored for radix-4 and mixed-radix FFT computations is described. The processor has native support for power-of-two transform sizes. Several optimizations have been used to improve the energy-efficiency of the processor and experiments show that a programmable solution can possess energy-efficiency comparable to fixed-function ASICs.

Low-power twiddle factor unit for FFT computation

An integral part of FFT computation are the twiddle factors, which, in software implementations, are typically stored into RAM memory implying large memory footprint and power consumption. In this paper, we propose a novel twiddle factor generator based on reduced ROM tables. The unit supports both radix-4 and mixed-radix-4/2 FFT algorithms and several transform lengths. The unit operates at a rate of one factor per clock cycle.

Low-power application-specific FFT processor for LTE applications

In this paper, we describe a processor architecture tailored to mixed-radix4/2/3 FFT algorithm. The proposed design supports all FFT sizes, namely 128-2048/1536, required by the LTE applications. The processor is based on the Transport Triggered Architecture processor architecture, which was customized with a set of function units, designed especially for the application at hand. The processor has been synthesized on an ASIC technology and both energy-efficiency and performance have been evaluated. The developed processor is programmable but shows energy-efficiency comparable to fixed-function ASIC implementations.

Reducing processor energy consumption by compiler optimization

Purpose of embedded computing is to transform input data to output format. Functionality required to achieve this goal is therefore combination of operation executions on computing units and data transfers between those units. To avoid memory bottlenecks, processors use register files to store data during computation.

3G Long Term Evolution Baseband Processing with Application-Specific Processors

Data rates in the upcoming 3G long term evolution (LTE) standard will be manifold when compared to the current universal mobile telecommunications system. Implementing receivers conforming with the high-capacity transmission techniques is challenging due to the complexity and computational requirements of algorithms. In this study, the software defined radio (SDR) is targeted and the four essential baseband functions of the 3G LTE receiver, namely, list sphere decoding, fast Fourier transform, QR decomposition, and turbo decoding, are addressed and the functions are implemented as application specific processors (ASPs). As a result, the design space that describes the essential computational challenges of 3G LTE receivers is clarified and estimates of area, power, and interprocessor communication buffer requirements are presented.

Parallel Memory Architecture for Application-Specific Instruction-Set Processors

Many of the current applications used in battery powered devices are from digital signal processing, telecommunication, and multimedia domains. These applications typically set high requirements for computational performance and often parallelism is the key solution to meet the performance requirements. In order to exploit the parallel processing units, memory should be able to feed the data path with data. This calls for a memory organization supporting parallel memory accesses. In this paper, a conflict resolving parallel data memory system for application-specific instruction-set processors is described. The memory structure is generic and reusable to support various application-specific designs. The proposed memory system does not employ any predefined access format signals for memory addressing. The proposed parallel memory system is attached to an application-specific instruction-set processor core and comparison on area, power, and critical path are shown. The experiments show that significant power savings can be obtained by exploiting the parallel memory system instead of multi-port memory.

Low-power application-specific processor for FFT computations

In this paper, we describe a processor architecture tailored for radix-4 and mixed-radix FFT algorithms, which have lower arithmetic complexity than radix-2 algorithms. The processor is based on transport triggered architecture and several optimizations have been used to improve the energy-efficiency. The processor has been synthesized on a 130nm standard cell technology and analysis show that a programmable solution can possess energy-efficiency comparable to a fixed-function ASIC.