Teijo Lehtonen

Online Reconfigurable Self-Timed Links for Fault Tolerant NoC

We propose link structures for NoC that have properties for tolerating efficiently transient, intermittent, and permanent errors. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. The protection against transient errors is realized using Hamming coding and interleaving for error detection and retransmission as the recovery method. We introduce two approaches for tackling the intermittent and permanent errors. In the first approach, spare wires are introduced together with reconfiguration circuitry. The other approach uses time redundancy, the transmission is split into two parts, where the data is doubled. In both structures the presence of permanent or intermittent errors is monitored by analyzing previous error syndromes. The links are based on self-timed signaling in which the handshake signals are protected using triple modular redundancy. We present the structures, operation, and designs for the different components of the links. The fault tolerance properties are analyzed using a fault model containing temporary, intermittent, and permanent faults that occur both as bursts and as single faults. The results show a considerable enhancement in the fault tolerance at the cost of performance and area, and with only a slight increase in power consumption.

Agile methods for embedded systems development - a literature review and a mapping study

There is a wide area of applications that use embedded systems, and the number of such systems keeps growing. The required functionality and complexity of embedded systems are also constantly increasing, and development of such products is becoming increasingly harder. This requires new thinking on the product development processes, and one such emerging philosophy is the agile methods. These methods were created by the software engineering community where they are commonly used. Since then, they have been adopted in embedded systems development; however, whether they can improve the embedded systems product development processes remains an open question. This study aims to bring forth what is known about agile methods in embedded systems development and to find out if agile practices are suitable in this domain and what evidence is there to support the findings. We conducted a literature review and a mapping study to answer these questions. The scope of this study is not only limited to embedded software development, but also to embedded hardware and integrated circuits. We have found that agile methods can be used in the embedded domain, but the methods and practices need to be adapted to suit the more constrained field of embedded product development. Furthermore, the field of embedded product development has wide diversity of products with different needs and domain-specific problems so that no single method is applicable, but rather many methods and practices are needed for different situations.

High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling

High-performance long-range NoC link enables efficient implementation of network-on-chip topologies which inherently require high-performance long-distance point-to-point communication such as torus and fat-tree structures. In addition, the performance of other topologies, such as mesh, can be improved by using high-performance link between few selected remote nodes. We presented novel implementation of high-performance long-range NoC link based on multilevel current-mode signaling and delay-insensitive two-phase 1-of-4 encoding. Current-mode signaling reduces the communication latency of long wires significantly compared to voltage-mode signaling, making it possible to achieve high throughput without pipelining and/or using repeaters. The performance of the proposed multilevel current-mode interconnect is analyzed and compared with two reference voltage mode interconnects. These two reference interconnects are designed using two-phase 1-of-4 encoded voltage-mode signaling, one with pipeline stages and the other using optimal repeater insertion. The proposed multilevel current-mode interconnect achieves higher throughput and lower latency than the two reference interconnects. Its throughput at 8 mm wire length is 1.222 GWord/s which is 1.58 and 1.89 times higher than the pipelined and optimal repeater insertion interconnects, respectively. Furthermore, its power consumption is less than the optimal repeater insertion voltage-mode interconnect, at 10 mm wire length its power consumption is 0.75 mW while the reference repeater insertion interconnect is 1.066 mW. The effect of crosstalk is analyzed using four-bit parallel data transfer with the best-case and worst-case switching patterns and a transmission line model which has both capacitive coupling and inductive coupling.

Analysis of forward error correction methods for nanoscale networks-on-chip

The amount of errors in future nanoscale technologies is expected to increase dramatically when compared to technologies that have line width larger than 90 nm. In nanoscale CMOS circuits fault tolerance is one of the most important design constraints to sustain system reliability at an acceptable level. We analyze different error correcting coding methods for on-chip communication networks of future nanoscale multiprocessor systems. The implemented communication circuits are compared in terms of error correction capability, circuit area and power consumption. In addition, performance of implemented systems is evaluated under different error scenarios by taking into account variable number of single bit errors, burst errors, and their combinations.

Fault-tolerant Routing Approach for Reconfigurable Networks-on-Chip

We introduce fault-tolerant on-chip routing philosophy for two-dimensional meshes. It is an extension to the concept of packet connected circuit, PCC. In order to increase reliability we have designed an automatic rerouting property to a single switch node and added return channel to the communication route. An autonomic routing switch node is modeled asynchronously and implemented using Haste language. The logical functionality of routing is illustrated as a single study case in 7*8 mesh. The routing success is further analyzed in congesting and faulty environment

Agile principles in the embedded system development

Agile manifesto with its four values and 12 principles provides widely accepted definition of agile. Agile methods have been actively used in software engineering and other fields are starting to utilize agile development methods as well. Embedded system development combines software, hardware and mechanical engineering activities and thus has some characteristics and constrains which are not found in pure software engineering. These constraints have earlier been described to be leading to some reinterpretation of agile practices. However, understanding how these constraints affect the applicability of agile philosophy in embedded domain has not yet been systematically analyzed. Here we will discuss about agile methods and its applicability in embedded system development through the 12 principles of agile manifesto. We aim to capture the philosophy of agile rather than only individual practices, by presenting redefined principles for embedded system development.

Agile methods in embedded system development

Examines three cases on applying agile practices into embedded system development.Visibility of work and system-wide understanding increased.Improved communication diminished the need for internal documentation.Slow hardware development and specialization of team members challenged agile methods.If not possible to present working product, visualize the progress in other ways. Agile methods are widely utilized in software development but their usage in embedded system development is often limited to software. A case study of three industrial cases was carried out to understand how to tailor agile methods effectively including also hardware development.Agile practices, mostly derived from Scrum, were tailored to fit the needs of each team and the method development was closely followed. Surveys conducted in the beginning and in the end of the cases were compared and complemented with interviews to understand the new working methods and their effects.Case evidence shows that interdependencies between work of each developer were taken into account better, visibility over the whole product increased and need for internal documentation diminished due to improved communication, but dividing hardware tasks into iterations was experienced difficult. With some tailoring, agile practices are beneficial also in the embedded system development.To successfully adopt agile methods into embedded system development, the team must consist of all the project members, the natural cycle lengths of different disciplines and different knowledge between the developers must be accepted and built upon, and the progress of the product must be presented or visualized in the end of each iteration.

Comparison of 130 nm technology 6T and 8T SRAM cell designs for Near-Threshold operation

Power consumption is an important aspect of almost any electrical device design. Near-Threshold Computing (NTC) is a voltage scaling technique that makes it possible to reduce the power consumption of CMOS devices with the cost of speed and reliability. We are using NTC to design low-power cache memory circuit for a low-performance sensor-based system. Caches consume noteworthy portions of power and area of this kind of systems, and therefore reducing their power consumption has a meaningful impact on the overall power consumption of the whole system. In this paper, 8T SRAM and 6T SRAM memory cells are compared in order to establish guidelines for choosing SRAM cell constructions for NTC systems. 8T SRAM is traditionally concerned as a more reliable memory cell, but we have managed to design 6T SRAM which executes read operation with an acceptable reliability; read being the most vulnerable operation of conventional 6T SRAM cell. Also, our 6T SRAM cell has 31% smaller area and smaller power consumption.

Simulations on 130 nm technology 6T SRAM cell for Near-Threshold operation

In the field of IC technologies, there is a constant demand for energy efficiency solutions. Near-Threshold Computing (NTC) is a technique that reduces energy consumption of IC devices, but it also makes them slower. We are applying NTC to a device constructed in 130 nm CMOS technology in the purpose of designing reasonably priced low-power IC devices suitable for low performance applications. In this paper, we concentrate on how a conventional 6T SRAM cell behaves in NTC use. Memory consumes a considerable portion of area and energy of a common IC system, and therefore it is a good target for optimizing with low-energy solutions. Applying NTC to 6T SRAM is not as straightforward as merely using lower supply voltage and slower clock speed; transistor sizes inside the memory cell have to be carefully considered to make the memory reliable. Two inner NMOS transistors in 6T SRAM cell play an important role; by doubling their widths from the minimum, the reliability and the static energy consumption are improved considerably. Overall, NTC makes it possible to achieve notable savings in the energy consumption of 6T SRAM cell.

Augmented reality: towards an ethical fantasy?

In this paper augmented reality solution development is analysed from an ethical perspective. The paper aims to be a guide on which different aspects of augmented reality and mixed reality development must at least be taken into account when adopting this emerging technology to counter ethically suspicious and malicious consequences which may cause harm amongst the different stakeholders. The analysis consist on both possible direct and collateral consequences of careless augmented reality system development where e.g. privacy, equality, data ownership and other forms of misuse are covered. The topics handled include direct consequences in the form of surveillance and other private and governmental use of augmented reality data, peer surveillance and sousveillance, ownership of data about ourselves, on top of such unintended consequences as augmented reality applications not acknowledging people of darker complexions or using augmented reality applications for even more effective bullying than current applications offer. Wider public discourse on the various current and potential uses of augmented reality applications is needed for the public to understand the direct and collateral consequences and for the legislators to make informed decisions on laws and policies governing augmented reality application usage.