Tertulien Ndjountche

Dynamic analog resonator-based adaptive filters

Dynamic analog building blocks (integrator, tunable gain stage) with high performance are proposed and analyzed. They exhibit low sensitivities to the component non-idealities (amplifier DC gain, amplifier and multiplier offset voltage, ...) and operate in double-sampled mode. Issues concerning the design of resonator based adaptive filters using the proposed structures are discussed. Numerical results obtained from a proof-of-concept prototype validate the proposed design method.

A CMOS front-end architecture for hard-disk drive read-channel equalizer

The functional characteristics and design challenges associated with the different building blocks of a CMOS front-end architecture for hard disk drive read-channel equalizer are presented. These include the mixed-signal design of a variable gain amplifier, a continuous-time low-pass filter, data converters and clock generation and recovery circuits. With a realistic computer model of the system, the analysis of structural variations and effects of component nonidealities becomes feasible. Numerical results show that circuit techniques that minimize sensitivity to power-supply and substrate noise, while maintaining the power dissipation and parameter tuning range are critical.

Design of a high-frequency second-order /spl Delta//spl Sigma/ modulator

As the minimum feature size of VLSI technologies scales down, more of the signal processing tasks are performed in the digital domain, making the analog-to-digital converter (ADC) design critical. High speed designs can be achieved by using oversampling ADC structures. At high sampling rates, the resolution appears to be limited by amplifier settling requirements. Design techniques to improve the ADC performance are presented. The proposed modulator structure uses the double-sampled technique, which increases by a factor of two the maximum speed of operation and correctly operates even with low DC gain amplifiers.

Image restoration: The wavelet-based approach

Wavelet-based techniques are suitable for recovering a signal corrupted by noise. The time- and frequency-localization capabilities of wavelets provide better noise reduction and less signal distortion than conventional filtering methods. The noise reduction technique used in this paper is based on the hidden Markov model (HMM) structure, which can efficiently shape the statistical characteristics of practical data. As confirmed by numerical results, the HMM based approach provides a significant performance improvement over competing methods.

A Mixed-Signal Equalizer Structure for Magnetic Storage Read Channels

Design techniques for read channel equalizers used in magnetic recording systems are presented. The equalization is based on a multi-level dual decision feedback architecture. The signal processing at low power and high speed is realized by using a continuous-time adaptive forward filter with an infinite impulse response. Furthermore, circuit structures with reduced offset-voltage sensitivities are developed for the equalizer implementation. As a result, the data rate in the intended application can be greater than 200 Mbits/s.

A Digital Adaptive Filter Architecture for Hard-Disk Drive Read Channels

With the increasing recording densities, adaptive equalizers used in disk-drive read channels have to operate at high frequencies. Using traditional design techniques, a compromise has to be made between speed, power, latency and area of the chip. The proposed equalizer is based on an adaptive lattice filter with an improved stability and low-sensitivity to round-off noise due to the orthogonality between internal states. An increase of speed and a reduction of power consumption are achieved in the resulting structure by using high-speed and low-power multiplier architectures based on an improved partial product encoding and pipeline stages to reduce the length of critical paths.

A low-power and high-speed equalizer for magnetic storage read channels

Design techniques for read channel equalizers used in magnetic recording systems are presented. The equalization is based on a multi-level dual decision feedback architecture. The signal processing at low power and high speed is realized by using a continuous-time adaptive forward filter with an infinite impulse response. Furthermore, circuit structures with reduced offset-voltage sensitivities are developed for the equalizer implementation. As a result, the data rate in the intended application can be greater than 200 Mbits/s.

A 1.5 V VLSI circuit for the co-channel signal separation

In analog implementations of adaptive algorithms, limited voltage ranges and inevitable DC offset voltages that arise in the learning circuit seriously degrade the convergence performance. Using the circuit structures proposed in the paper, these problems are eliminated and the learning characteristic of the resulting network is improved. The test results are obtained from a structure with two channels using a stochastic gradient algorithm in order to minimize the cost function defined as the output signal cross-correlation. This algorithm allows the identification of the channels and the reconstruction of the signals so long as the signals are L/sub 2/ integrable.