Teruo Sasagawa

Process study and optimization for fabrication of poly‐Si thin‐film transistors on plastic substrates

— A complete poly-Si thin-film transistor (TFT) on plastic process has been optimized to produce TFT arrays for active-matrix displays. We present a detailed study of the poly-Si crystallization process, a mechanism for protecting the plastic substrate from the pulsed laser used to crystallize the silicon, and a high-performance low-temperature gate dielectric film. Poly-Si grain sizes and the corresponding TFT performance have been measured for a range of excimer-laser crystallization fluences near the full-melt threshold, allowing optimization of the laser-crystallization process. A Bragg reflector stack has been embedded in the plastic coating layers; its effectiveness in protecting the plastic from the excimer-laser pulse is described. Finally, we describe a plasma pre-oxidation step, which has been added to a low-temperature (<100°C) gate dielectric film deposition process to dramatically improve the electrical properties of the gate dielectric. These processes have been integrated into a complete poly-Si TFT on plastic fabrication process, which produces PMOS TFTs with mobilities of 66 cm2 /V-sec, threshold voltages of −3.5 V, and off currents of approximately 1 pA per micron of gate width.