Teruyoshi Mihara

A surge-free intelligent power device specific to automotive high side switches

A novel type of intelligent power device (IPD), which is suitable for automotive monolithic high side switch with high current capability, is presented. An integration of a vertical-power DMOSFET and planar MOS IC devices is performed by the newly developed junction-isolation technique using only one epitaxial growth. The isolation voltage of 80 V has been obtained, which is large enough for automotive IPDs if they are protected against high voltage transients on the battery line. A rugged vertical DMOSFET (VDMOS) has also been developed for this IPD. It has a cellular Zener diode between its source and drain, which prevents the secondary breakdown of parasitic bipolar transistor, and the resulting avalanche capability enhancement is more than an order of magnitude. This VDMOS is used for both output power device and protection device for low-voltage MOS circuitry, which makes the IPD free from any transients in the automobile without the need for external protection. >

A DMOSFET having a cell array field ring for improving avalanche capability

A DMOSFET having a cell array field ring for improving avalanche capability is described. When shrinking the cell size of the DMOSFET, the cell array field ring is effective for unifying the power dissipation over the chip surface during avalanche breakdown. The power dissipation of this durable DMOSFET is uniform over the chip surface during avalanche breakdown. Its avalanche failure power is around 127 W/mm/sup 2/ for a 1-ms pulse width and tends toward a tau /sup -1/2/ dependence. A failure mechanism during avalanche breakdown is also studied. The critical failure temperature of this DMOSFET is only 50 K lower than the intrinsic temperature for the N-drain regions.<<ETX>>

Low on-resistance power LDMOSFET using double metal process technology

A low on-resistance lateral power FET which is suitable for the H-bridge motorcontrol IPD (intelligent power device) for automatic applications is described. The LDMOSFET was fabricated using the double metal process technology with a hexagonal pattern layout which increases the cell density. The device with cell density as high as 5.1 million cells/in/sup 2/ has a specific on-resistance of 1.15 m Omega -cm/sup 2/ under pulsed drain bias conditions, and the reverse blocking voltage is 42 V. This on-resistance represents the lowest among the lateral type power FETs with similar blocking voltage.<<ETX>>

Low on-resistance LDMOSFETs with DSS (a drain window surrounded by source windows) pattern layout

This paper describes new low on-resistance lateral DMOSFETs having a DSS (a Drain window Surrounded by Source windows) pattern layout. The new DSS pattern layout increases the source cell density to as high as 4 million cells/inch/sup 2/ thus minimizing the channel-resistance of the devices. A specific on-resistance of 0.65 m/spl Omega//spl middot/cm/sup 2/ with a blocking voltage of 36 V is obtained. The DSS LDMOSFETs are suitable for intelligent power devices (IPDs) that provide multiple outputs.

Verification of LLC resonant converter applied a current-balancing high-frequency transformer with multi-output windings

DC-DC converters of hybrid vehicles and electric vehicles are required to become smaller and lighter for building roomy and light weight EV. High-frequency switching can be used to miniaturize DC-DC converter. However, the influence of the skin effect and the eddy current become large. Parallel operation of converter is often for current applications using multiple winding transformers in order to reduce of skin effect. However, it is difficult to equalize the each current of converter due to unbalance of winding resistance, drop voltage of diodes and so on. In this paper, the parallel LLC converter applied a current-balancing high-frequency transformer is proposed. The proposed converter can realize nearly equal current even if the stray impedance of secondary circuit of LLC are unbalanced.