Tetsuji Tamura

Distributed On-chip Power Supply Noise Characterization of the Cell Broadband Engine

Noise characterization of the 65 nm multicore Cell Broadband Enginetrade (Cell/B.E.)* processor was performed using highly configurable workloads and selective stimulation of identical cores to study noise distribution throughout the chip. On-chip power supply noise propagation velocity and attenuation were found to be influenced by chip/package resonance in the power distribution system. Hypothesis for this phenomenon is proposed.

Thermal Development, Modeling and Characterization of the Cell Processor Module

Optimal package thermal design for todays high power processors is critical to meet demanding performance, cost, and reliability objectives. This paper describes the thermal characterization and development of the first generation CELL processor, developed jointly by Sony, Toshiba and IBM. The package not only provides the very high bandwidth necessary for electrical performance, but also achieves low thermal resistance to dissipate high power and maintain low die temperatures with superior reliability. The focus of the paper is the first level package. The target thermal resistance for the package is explained as determined from detailed 2nd level modeling and novel power map calculation and validation techniques are discussed. Thermal and mechanical modeling are used characterize the effects of the thermal interface material (TIM) on the thermal performance and mechanical response of the package. The thermal test strategy and the TIM characterization techniques are described. In summary, the paper describes the novel thermal modeling and characterization methodology used in the design process, allowing high heat flux in a low cost system application