Tetsuya Mizuguchi

A Novel Resistance Memory with High Scalability and Nanosecond Switching

We report a novel nonvolatile dual-layered electrolytic resistance memory composed of a conductive Cu ion activated layer and a thin insulator for the first time. An ON/OFF mechanism of this new type memory is postulated as follows: Cu ions pierce through the insulator layer by applied electric field, the ions form a Cu conductive bridge in the insulator layer, and this bridge dissolves back to the ion activated layer when the field is reversed. The 4 kbit memory array with 1T-1R cell structure was fabricated based on 180 nm CMOS process. Set/reset pulses were 5 ns, 110 muA and 1 ns, 125 muA, respectively. Those conditions provide large set/reset resistance ratio of over 2 orders of magnitude and satisfactory retention. Essential characteristics for high capacity memories including superb scalability down to 20 nmphi, sufficient endurance up to 107 cycles and preliminary data for 4-level memory are also presented. These characteristics promise the memory being the next generation high capacity nonvolatile memory even before the scaling limitation of flash memories is encountered.

Magnetoresistive random access memory operation error by thermally activated reversal (invited)

The reliability in magnetoresistive random access memory (MRAM) write operation was investigated for both toggle and asteroid memory chips developed with 0.18μm CMOS process. Thermally activated magnetization reversal, being the dominant origin of the intrinsic write error, was studied theoretically and experimentally. For asteroid MRAM, the bit line or word line disturbing error on half selected bits was proved to have significant effect on the write operation margin, even in the ideal case free from bit-to-bit switching field distribution and the hysteresis loop shift. For toggle MRAM, on the other hand, the dominant origin of the error occurs for selected bits, although its impact is much smaller than in the case of asteroid MRAM. As was expected from the estimation based on the single domain model, more than 10mA operation margin with the error rate of <10−9, which is sufficiently small for semiconductor IC memory, was achieved for the toggle MRAM.

MRAM with improved magnetic tunnel junction material

Summary form only given. Increasing output and decreasing switching field distribution are very important for the development of magnetic tunnel junction (MTJ) materials, in order to achieve a high capacity MRAM. We introduce an amorphous MTJ material with excellent characteristics, which is evaluated through the MRAM/MTJ test element groups (TEG) with a MOS circuit.

The thin film head for VCR

We have investigated a thin film head for VCR application whose structure has a long depth and a gap surface that is perpendicular to the substrate. We made a test device that has a CoZr amorphous thin film core. The conductor is a helicoid that is wound three-dimensionally around the core and is fabricated by thin film processes. The thin film head obtained larger normalized output voltage by track width and inductance than a MIG head between 1 to 10 MHz. >

Characteristics of NiFe/CuNi multilayer GMR sensors for vertical GMR heads

By using a novel NiFeCr buffer layer, a substantial improvement in a GMR ratio of 4.5% with a low saturation field of 19 Oe was obtained. The structure of all GMR multilayers was glass/NiFeCr[5 nm]/NiFe[1.7 nm]/(CuNi[2.3 nm]/NiFe[1.7 nm])3/Cr[2 nm]. The change in sheet resistance was 0.8 Ohms/square. Magnetoresistances, current density effects and transfer curves for 2, 1, and 0.5 micron trackwidth GMR sensors of these structures are described. At a trackwidth of 0.5 /spl mu/m, maximum field sensitivity of 215 /spl mu/m V/Oe was obtained with a sensor length of 2 /spl mu/m, a sense current of 3 mA. No degradation in magnetoresistance of sheet CMR was found after annealing at 270/spl deg/C. However, sensor-size dependent thermal degradation was observed.

Sensor design of vertical type GMR head

We previously reported that the vertical GMR (V-GMR) head can be used for a high-density recording head. However, special design rules are required because the head has a different geometry from the conventional head. We discuss the optimum design of the V-GMR head. We report the technologies and materials required to produce the V-GMR head. Using computer simulations and wafer level experiments, we confirmed that the optimized V-GMR head can he used for more than 40 Gbit/in/sup 2/ areal density.

Improvement of GMR characteristics of spin-valve films with a novel free layer

In order to obtain a large change in resistance, a free layer structure of Ta/NiFeTa/CoFe in spin-valve films was examined. The magnetoresistance properties and the thermal stabilities varied with the resistivity of NiFeTa and the crystallographic texture of the spin-valve film. For the structure of glass/Ta[5 nm]/(NiFe)/sub 88.5/Ta/sub 11.5/[5 nm]/CoFe[2.5 nm]/Cu[2.75 nm]/CoFe[2.5 nm]/IrMn[6 nm]/Ta[5 nm], the change in sheet resistance of 2.3 /spl Omega///spl square/ (MR ratio of 12.3%) and 2.0 /spl Omega///spl square/ (9.5%) were obtained before and after annealing at 280/spl deg/C for 5 hours, respectively.

Fabrication of spin-valve sensors with quarter micron trackwidth using a double-layer resist system

We report the fabrication methods of vertical type spin-valve (SV) sensors with a quarter micron trackwidth using electron beam lithography and ion beam etching. A double-layer resist system which simultaneously solves the problems of resist residuals and the redepositions have been investigated. This method was successfully applied to fabricate IrMn-SV sensors with a 250 nm trackwidth. Transfer curve measurements showed degradation of GMR ratio from 11% to 7% after fabrication. However, this degradation was not thought inherent to this process.

A cross point Cu-ReRAM with a novel OTS selector for storage class memory applications

This paper demonstrates a cross point Cu based Resistive Random Access Memory (Cu-ReRAM) technology suitable for Storage Class Memory (SCM) applications. Two key technologies have been developed for large capacity of 100Gb-class SCM with 100 ns program speed and 10M cycles of program endurance. One is tight resistance distributions of Cu-ReRAM by inserting a barrier layer to prevent excess intermixing. The other is a novel Boron and Carbon (BC) based Ovonic Threshold Switch (OTS) selector which meets requirements for large cross point arrays with low leakage current, low threshold voltage variability, and high endurance.