Tetsuya Tanabe

A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture

A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4-/spl mu/m CMOS technology is used to fabricate the chip.

A 32-bank 256-Mb DRAM with cache and TAG

Megabit DRAM design has recently focused both on high data transfer rates and battery operation. To meet the demand for high data-rate memory, this synchronously-operated 32-bank 256 Mb CMOS DRAM has sense amplifier (SA) cache strips and TAGs. The key techniques are: (1) high bit-rate cache operation achieved by 32 8 Mb memory banks supported by the bank-associated shared SA caches and TAG blocks embedded in row decoders, (2) a reduced RAS latency achieved during a bank hit cycle by a bank interleaving scheme, (3) high stability bank control by phase alignment of high-rate timing pulses, and (4) current sensing data-bus amplifier (CSA) scheme with a voltage-controlled negative conductance (VCNC) circuit. >

On-wafer BIST of a 200 Gb/s failed-bit search for 1 Gb DRAM

For giga-scale DRAM, it is important to reduce test time. Built-in self-test (BIST) for a 1 Gb DRAM realizes a 200 Gb/s failed-search for repair with redundancy and reduces on-wafer function test time to less than 1/100 that of a bit-by-bit test. An array architecture, with very-long word (VLW) transfer circuits, probes DRAM internal nodes and transfers a 4 kb pass or fail bit-map. An on-wafer test management unit (TMU), includes a failed-address aligner (FAA) that converts a transferred 4 kb VLW into two streams of l0 b/spl times/l6 w(word) failed-address data. Major BIST functions are continuous test vector generation and failed-bit detection. Line test widely known as a failed-bit detection method, reduces the final test time. However, line-test circuits are not adequate to search and identify failed-bits in DRAM wafer test. In this on-wafer BIST, if failed-bits are detected, the failed-addresses are directly sent to an external tester, shortening failed-bit search time to within the same order as line-test time. The DRAM and two TMUs (UP and DN) concurrently operate on a wafer. The TMUs are on both sides of the DRAM, partitioned by scribe lines.