Theodore H. Kaskalis

A RECONFIGURABLE SYSTOLIC TORUS FOR ITERATIVE MATRIX OPERATIONS

This paper discusses the efficient implementation of iterative matrix operations on application specific processor arrays. Recursive equations, frequently met in a wide range of problems, can be solved through a new systolic structure, the Reconfigurable Systolic Torus, in almost optimal Area and Time requirements. Moreover, flexibility is maintained with no demand of complex instruction sets or extensive control units implemented inside the systolic cells. The general design together with the computation schedules are presented and the description of this new structure is gradually built towards the satisfaction of some basic predefined criteria.

Data flow in a sensor system: Current state and challenges

This paper presents the basic data flow in a wireless sensor network based on the current literature of the area. The first step is to study exactly how information and different data move in a system like this. Various frameworks have been proposed to represent data move from one layer to another, in order to reach the end-user. After introducing the basic parts of a sensor network in section 1, we proceed to analyze two basic frameworks that present the data flow in such systems in the following two sections. These are distinguished in two types of layers: lower and upper. Section 4 discusses the middleware of a sensor network system, where SensorML and the appropriate ontologies play an important role in data exchange between the parts of the system. The conclusions drawn from this discussion lead to important open issues for further research, paving the way for appropriate study.

WIPE-a model for a Web-based database-driven environment for teaching programming

We describe a Web-based programming environment that serves for the teaching of the basic principles of programming. The environment is accessible via the Internet through a Web browser and uses a specially featured compiler to translate the source code of the programming language into a pseudo assembly code. Supplementary programming tools accompany the compiler and a database is used for storing the intermediate remits (i.e., the code students develop while trying to solve an exercise). In addition, there is a complete user, file and group management environment and a tool to automate the testing of the student solutions to programming exercises.

Systolic Artificial Neural Network prototyping using ptolemy

In this paper we present an example of how the ptolemy environment can be used constructively to implement and simulate a certain class of Artificial Neural Networks, called Associative Memories. Through graphical means, the user can easily obtain prototypes in a level high enough to be comprehensive and, at the same time, low enough to present the design complexity of a potential implementation. Moreover, the ability to simulate the functioning of the circuit ensures the correctness of an algorithm. A brief introduction to the Ptolemy environment is given and a step by step creation of a typical systolic based Discrete Autocorrelator circuit is then described. A hierarchical design method is followed and details are given about the correct reflection of the synchronous nature of systolic circuits and the dynamic schedule imposed by iteration convergence on typical dataflow executions.

Systolic Optimal Linear Associative Memory ANN Prototyping Using The Ptolemy Environment

This paper presents an example of how the Ptolemy environment can be used constructively to simulate prototypes of Artificial Neural Network algorithms, implemented by means of Systolic Array architectures. Initially, a number of well-known ANN algorithms, which all fall under the general concept of Associative Memory Artificial Neural Networks, is presented. Then, follows the discussion for the transformation and mapping of those algorithms onto a Linear Array Systolic architecture, capable of implementing all the discussed Associative Memory algorithms. Further, the Systolic Array architecture is designed and simulated using the Ptolemy Environment. Through graphical means, the user can easily obtain systolic circuit prototypes, at a level high enough to be comprehensive and, at the same time, low enough to present the design complexity of a potential hardware implementation. Finally, the ability to simulate the functioning of the Systolic Artificial Neural Network circuit ensures the correctness of the initial algorithms, as well as of the systematic transformation and mapping technique.

Systolic array prototyping using the Ptolemy environment

In this paper we present an example of how the Ptolemy environment can be used constructively to implement and simulate systolic algorithms and architectures. Through graphical means, the user can easily obtain systolic circuit prototypes in a level high enough to be comprehensive and, at the same time, low enough to present the design complexity of a potential implementation. Moreover, the ability to simulate the functioning of the circuit ensures the correctness of a systolic algorithm. A brief introduction to the Ptolemy environment is given and a step by step creation of two typical systolic array designs is then described. A hierarchical design method is followed and details are given about the correct reflection of the synchronous nature of systolic circuits on typical dataflow executions.

Matrix Polynomial Computations Using the Reconfigurable Systolic Torus

Publisher Summary The solution of various types of equations appearing in many mathematical models, dynamic probabilistic systems, and in stochastic and control theory often requires the calculation of distinct matrix functions. A wide range of matrix functions including matrix exponentials, inversions, and square roots can be transformed to matrix polynomials through taylor series expansions. This chapter considers an efficient computation of such matrix polynomials through the exploitation of their recursive nature. The reconfigurable systolic torus is proposed for its ability to implement iterative equations of various forms. Moreover, the chapter presents a detailed example of the matrix exponential realization together with the scaling and squaring method. It also discusses the general design concepts of the reconfigurable systolic torus and presents the algorithmic steps needed for the implementation. The area and time requirements, together with the accomplished utilization percentage, conclude the presentation.