Thierry Cornu

Special-purpose digital hardware for neural networks: an architectural survey

This paper presents a survey of digital systems to implement neural networks. We consider two basic options for designing these systems: parallel systems with standard digital components and parallel systems with custom processors. We describe many examples under each option, with an emphasis on commercially available systems. We report a first trend toward more general architectures and a second trend toward simple and fast structures. We discuss our experience in running a small ANN problem on two of these machines. After a reasonable programming effort, we obtain good convergence, but most of the training times are actually slower or moderately faster than on a serial workstation. We conclude that it is important to chose ones problems carefully, and that support software and in general, system integration, is only beginning to reach the level of versatility that many researchers will require.

Design, Implementation, and Test of a Multi-Model Systolic Neural-Network Accelerator

Keywords: neurone ; Non-Linear Modelling ; Neural Network Reference LANOS-CONF-1994-018 Record created on 2004-12-03, modified on 2016-08-08

Performance of digital neuro-computers

This paper deals with performance measurement and evaluation of digital neuro-computers. We discuss the constraints introduced by hardware implementations. A revisited definition of computer speed-up is then proposed, taking into account both the traditional notion of parallelization speed-up and the algorithmic precision of the machines. Finally we show, on the example of the Kohonen feature map algorithm, how a fair benchmarking procedure can be established to evaluate digital neuro-computers more significantly than using the traditional Mcups metric.

Contention in the Cray T3D Communication Network

This paper studies the effect of contention on communication times in the interconnection network of the Cray T3D computer. We propose a method to measure average communication time as a function of the utilization rate of the communication network; the results are presented. It is shown that locality of communications help reduce contention effects and can therefore have a non-negligible impact on the performance of the system.

Design and implementation of a parallel cellular language for MIMD architectures

In this paper we present a new language, called ParCeL-1, intended to make easier the implementation of computation-intensive and artificial intelligence applications on highly parallel MIMD architectures. The computational model of ParCeL-1 is object-oriented and synchronous, based on virtual processors called cells that compute and communicate alternately. The current prototype is implemented on several multi-processor systems (Cray T3D, Intel Paragon, Telmat T-Node, workstation networks using PVM, and SGI Power Challenge Array). Several applications written in ParCeL-1 are described, together with their performances obtained on a 256-processor Cray T3D.

ParCeL-1: a parallel programming language based on autonomous and synchronous actors

In this paper we present a new language, called ParCeL-1, intended to make easier the implementation of computation-intensive applications on highly parallel MIMD architectures. The computational model of ParCeL-1 is object-oriented and synchronous. The current prototype is implemented on several multi-processor systems (Cray T3D, Intel Paragon, Telmat T-Node and workstation networks using PVM). Benchmarks are presented for several parallel programs.

Chapter 2 - An Abstract Machine for Implementing Connectionist and Hybrid Systems on Multi-processor Architectures

Abstract The interest in new hybrid AI models, both symbolic and numeric, is currently increasing due to the complementary capabilities of these models. We present here the Cellular Abstract Machine (CAM), a tool for building such hybrid systems, taking the form of heterogeneous networks of cooperating agents (here called cells ). Several AI applications have been written using the CAM, including a sample hybrid system. The CAM is implemented over a parallel architecture (a Transputer network). We give here the basic principles of the parallel implementation.

Performance Analysis of a Parallel Program for Wave Propagation Simulation

During the last decade, performance prediction has been repeatedly quoted as a key factor to developing parallel systems. Predicting the performance of a parallel program as a function of the number of processors and of the problem size is crucial for choosing the best hardware configuration and for tuning various parameters. This paper presents a method for achieving performance analysis for parallel irregular applications. The model is closely related to the Bulk Synchronous Programming (BSP) model [4]. It is based on the measurement of basic communication and computation routines. The computational workload of each processor and the load imbalance are modeled analytically. The method is used for predicting the performances of ParFlow++, an irregular, parallel radio-wave propagation algorithm.

Application development under ParCeL-1

In this paper, we present several kinds of programs developed in a new parallel language, ParCeL-1. This language is based on autonomous actors that compute concurrently as virtual processors. The applications we present here cover various domains of interest to Artificial Intelligence, especially tree search and connectionist programming. We present general methods to develop such kinds of algorithms in ParCeL-1. Then we emphasize several rules that should be followed to write efficient parallel programs. Finally, we describe the performances of these applications on two parallel computers.

ParCeL-1: a parallel language based on autonomous agents for connectionist and AI applications

We present a new language called ParCeL-1, dedicated to connectionist and explicitly parallel AI programming. ParCeL-1 is a language based on agents, similar to actor languages. Its agents are autonomous and follow a computational model in which the communications are non-blocking and the communication scheme is explicit. ParCeL-1 has a parallel implementation and runs on several multiprocessor architectures. We give an example of connectionist programming (the Kohonen map) and show several performance results on a transputer based multiprocessor architecture and on the Cray T3D parallel computer.