Thierry Fautier

DIVA: a MPEG1 video decoder for interactive applications

ISO/MPEG has specified an algorithm for compression of video sequences at 1.5 Mbit/s. Meanwhile, additional features must be provided by the decoding system in order to build interactive applications. Support of special modes (slow, reverse, fast) and direct interfacing with graphical and video systems give an added value to the global system. In this paper, we describe a one chip MPEG1 video decoder, DIVA (Decoder for Interactive Video Applications) dedicated to interactive applications. It implements the decoding of MPEG core bitstream and is able to decode a compressed video bitstream at up to 5 Mbit/s. The architecture is organized around a single memory bank of DRAMs used in fast page mode to reach the performances required by the algorithm. After decoding, output pictures are resampled at CCIR 601 resolution and can be generated at 13.5 MHz for interlaced systems or at 25.175 MHz for computer (VGA) PC systems. An instruction set was developed in order to drive the chip so that an application can load instructions in the decoder well in advance before their execution, thus releasing the CPU from the scheduling task. DIVA was designed with an ASIC approach in a 0.8 micron technology. The chip contains 600,000 transistors in a die size of 11 X 11 sq mm and dissipates 1.3 Watt at 27 MHz.