Thomas A. Horvath

Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications

This paper describes the hardware and software ecosystem encompassing the brain-inspired TrueNorth processor – a 70mW reconfigurable silicon chip with 1 million neurons, 256 million synapses, and 4096 parallel and distributed neural cores. For systems, we present a scale-out system loosely coupling 16 single-chip boards and a scale-up system tightly integrating 16 chips in a 4 × 4 configuration by exploiting TrueNorths native tiling. For software, we present an end-to-end ecosystem consisting of a simulator, a programming language, an integrated programming environment, a library of algorithms and applications, firmware, tools for deep learning, a teaching curriculum, and cloud enablement. For the scale-up systems we summarize our approach to physical placement of neural network, to reduce intra- and inter-chip network traffic. The ecosystem is in use at over 30 universities and government/corporate labs. Our platform is a substrate for a spectrum of applications from mobile and embedded computing to cloud and supercomputers.

Hardware architecture to accelerate the belief propagation algorithm for a Wyner-Ziv decoder

Wyner-Ziv based video codecs reverse the processing complexity between encoders and decoders such that the complexity of the encoder can be significantly reduced at the expense of highly complex decoders requiring hardware accelerators to achieve real time performance. In this paper we describe a flexible hardware architecture for processing the Belief Propagation algorithm in a real time Wyner-Ziv video decoder for several hundred, very large, Low Density Parity Check (LDPC) codes. The proposed architecture features a hierarchical memory structure to provide a caching capability to overcome the high memory bandwidths needed to supply data to the processors. By taking advantage of the deterministic nature of LDPC codes to increase cache utilization, we are able to substantially reduce the size of expensive, high speed memory needed to support the processing of large codes compared to designs implementing a single layer memory structure.

A novel memory architecture to achieve minimal rounding/truncation errors for N dimensional image transformation

This paper describes a novel memory architecture to minimize truncation error for implementing N-Dimension decomposable transformation using consecutive one dimension (1D) transformation approach. The memory architecture utilizes the effective bit representation not only achieving minimal truncation error with a constrained memory size, but also minimizing memory size to fulfill a given accuracy requirement. A 8/spl times/8 2-D IDCT macro that used the proposed architecture is implemented. The cell count for the macro is 43 K cells and occupies 6 mm/sup 2/ using 0.5 /spl mu/m CMOS VLSI technology.