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Dive into the research topics where Thomas A. Piazza is active.

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Featured researches published by Thomas A. Piazza.


IEEE Micro | 2014

Haswell: The Fourth-Generation Intel Core Processor

Per Hammarlund; Alberto J. Martinez; Atiq Bajwa; David L. Hill; Erik G. Hallnor; Hong Jiang; Martin G. Dixon; Michael N. Derr; Mikal C. Hunsaker; Rajesh Kumar; Randy B. Osborne; Ravi Rajwar; Ronak Singhal; Reynold V. D'Sa; Robert S. Chappell; Shiv Kaushik; Srinivas Chennupaty; Stephan J. Jourdan; Steve H. Gunther; Thomas A. Piazza; Ted Burton

Haswell, Intels fourth-generation core processor architecture, delivers a range of client parts, a converged core for the client and server, and technologies used across many products. It uses an optimized version of Intel 22-nm process technology. Haswell provides enhancements in power-performance efficiency, power management, form factor and cost, core and uncore microarchitecture, and the cores instruction set.


international symposium on microarchitecture | 2001

ZR: A 3Dd API transparent technology for chunk rendering

Emile Hsieh; Vladimir Pentkovski; Thomas A. Piazza

This paper presents ZR (Zone Rendering), a 3D graphics technology that addresses ever-increasing bandwidth requirements using chunk rendering technique, and at the same time solves 3D API compatibility issues commonly associated with chunk rendering graphics devices. We apply a pipeline serialization technique to handle the cases causing compatibility issues. However, excessive frequency of serializations may offset the performance advantage of ZR. In order to manage potential performance problems we developed software and hardware techniques to optimize ZR performance for most events that might cause the serialization. Comprehensive validation experiments were conducted for popular 3D applications to show that after the optimizations the residual impact of the serialization is very small. Finally, using the results of Intel® 830 graphics, which implements ZR, we demonstrate that ZR provides significant 3D graphics performance improvement. This result is achieved within a limited bandwidth budget, and at the cost of modest micro-architectural changes to traditional graphics pipeline.


Operating Systems Review | 2011

Bothnia: a dual-personality extension to the Intel integrated graphics driver

Gautham N. Chinya; Jamison D. Collins; Perry H. Wang; Hong Jiang; Guei-Yuan Lueh; Thomas A. Piazza; Hong Wang

In this paper, we introduce Bothnia, an extension to the Intel production graphics driver to support a shared virtual memory heterogeneous multithreading programming model. With Bothnia, the Intel graphics device driver can support both the traditional 3D graphics rendering software stack and a new class of heterogeneous multithreaded applications, which can use both IA (Intel Architecture) CPU cores and Intel integrated Graphics and Media Accelerator (GMA) cores in the same virtual address space. We describe the necessary architectural supports in both IA CPU and the GMA cores and present a reference Bothnia implementation. For a set of GPU accelerated media applications on a PC platform with Intel Core 2 Duo CPU and the Intel integrated GMA X3000 running under the Windows XP operating system, Bothnia achieves an average speedup of 3.6x compared to using the GPU as a device, primarily due to Bothnias support for creation of shared virtual address space between heterogeneous threads of the same application spread on both IA CPU and GMA cores.


Archive | 2004

Memory arbiter with intelligent page gathering logic

Josh B. Mastronarde; Aditya Sreenivas; Thomas A. Piazza


Archive | 2002

Method and apparatus for pixel filtering using shared filter resource between overlay and texture mapping engines

David W. Watson; Kim A. Meinerth; Indraneel Ghosh; Thomas A. Piazza; Val G. Cook


Archive | 2002

Z-buffering techniques for graphics rendering

Thomas A. Piazza; Eric C. Samson


Archive | 2004

Render-cache controller for multithreading, multi-core graphics processor

Thomas A. Piazza; Prasoonkumar Surti


Archive | 2002

Method and apparatus for saving power and improving performance in a collapsable pipeline using gated clocks

Thomas A. Piazza


Archive | 2000

3-D rendering texture caching scheme

Michael Mantor; John Austin Carey; Ralph Clayton Taylor; Thomas A. Piazza; Jeffrey D. Potter; Angel E. Socarras


Archive | 1998

Method and apparatus for texture level of detail dithering

Thomas A. Piazza; Michael Mantor; Ralph Clayton Taylor; Steven Manno

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