Thomas Benner

Hardware-software cosynthesis for microcontrollers

The authors present a software-oriented approach to hardware-software partitioning which avoids restrictions on the software semantics as well as an iterative partitioning process based on hardware extraction controlled by a cost function. This process is used in Cosyma, an experimental cosynthesis system for embedded controllers. As an example, the extraction of coprocessors for loops is demonstrated. Results are presented for several benchmark designs.<<ETX>>

The COSYMA environment for hardware/software cosynthesis of small embedded systems

Abstract COSYMA is a platform for the investigation of hardware/software cosynthesis of small embedded systems. Target architecture is currently limited to processor-coprocessor configurations executing a single process or a system of communicating processes which are statically scheduled. Many aspects of cosynthesis such as automatic hardware/software partitioning, efficient hardware/software communication, timing and hardware overhead estimation and analysis, interdependence of different cosynthesis phases, data representation, etc., can successfully be investigated in this manageable domain. COSYMA covers the complete design flow from an input language similar to C down to netlist and object code. Current focus is on high performance data dominated systems, but first steps to incorporate control dominated subtasks can be presented. Using a specific high-level synthesis tool, the results show a considerable speedup of the resulting processor-coprocessor system even compared to modern RISC processors which is typically limited by memory bandwidth.

Fast timing analysis for hardware-software co-synthesis

At the current time, an iterative approach seems to be best suited for hardware/software partitioning in hardware/software co-synthesis with time constraints. To check the timing constraints, the iteration loop contains a timing analysis. Only computation time-intensive RT-level simulation provides sufficient timing precision for complex processor architectures. We present a hardware/software timing analysis, which comes close to the precision of an RT-level simulation in a fraction of the computation time and, thus, removes a bottleneck from iterative hardware/software co-synthesis. We present some results for our co-synthesis system COSYMA.<<ETX>>

Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis

Previously, we had presented the system COSYMA for hardware/software co-synthesis of small embedded controllers. Target system of COSYMA is a core processor with application specific co-processors. The system speedup for standard programs compared to a single 33MHz RISC processor solution with fast, single cycle access RAM was typically less than 2 due to restrictions in high-level co-processor synthesis, and incorrectly estimated back end tool performance, such as hardware synthesis, compiler optimization and communication optimization. Meanwhile, a high-level synthesis tool for high-performance co-processors in co-synthesis has been developed. This paper explains the requirements and the main features of the high-level synthesis sytem and its integration into COSYMA. The results show a speedup of 10 in most cases. Compared to the speedup, the co-processor size is very small.

The Cosyma System

This chapter gives an overview on Cosyma and is a complement to the existing literature in that it gives more tool and system specific information which gives a better impression of the whole system and is extremely helpful when using the system. More information, examples, the complete Cosyma system, a user manual, and a small library can be obtained from This chapter also summarizes the Cosyma extensions which will have been released by the time of book publication.

An approach to mixed systems co-synthesis

The paper presents an extension of co-synthesis for data dominated applications to include reactive processes. The extension allows for rate constraints as used in data dominated applications as well as minimum and maximum time constraints for communication and I/O which is required to define reactive behavior of control tasks. A co-synthesis approach is proposed which differentiates global process and communication scheduling, which is non preemptive, and local scheduling which includes a restricted interrupt controlled process invocation to extend the design space. Several user parameters allow design space exploration. The approach includes buffering, process pipelining and parallelization for control as well as for data dominated tasks on different levels of granularity. It supports inter process time constraints which span processes with different periods. The target architectures are heterogeneous systems consisting of multiple processors, hardware components, memories and different types of communication media.

Scalable performance scheduling for hardware-software cosynthesis

The paper presents a static process scheduling approach as a front-end to hardware-software cosynthesis of small embedded systems which allows global system optimization. Unlike earlier approaches, scheduling is executed before hardware definition assuming scalable system performance. Scheduling supports process communication and external timing requirements. We explain the algorithm and give results using an example.

A prototyping system for verification and evaluation in hardware-software cosynthesis

We present a system emulator for rapid prototyping of small embedded HW/SW-systems with hard timing constraints generated by a HW/SW cosynthesis system. It consists of a standard core processor and an application specific coprocessor, which is emulated by XILINX FPGAs. A byte slice architecture allows to emulate rather complex coprocessors. The system emulator supports the prototyping, debugging and time measurement in a comfortable way.

FPGA Based Prototyping for Verification and Evaluation in Hardware-Software Cosynthesis

COSYMA is a HW/SW-cosynthesis system for small embedded controllers. The final simulation of the COSYMA output leads to impractical computation time. Therefore, we decided to employ a hardware prototyping system. The HW/SW prototyping system consists of a SPARC processor, an FPGA-based coprocessor with HW/SW debugging features realized with a high speed microcontroller.