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Archive | 1979

Digital data processing system with interface adaptor having programmable, monitorable control register therein

Thomas H. Bennett; Earl F. Carlow; Edward C. Hepworth; Wilbur L. Mathys; William D. Mensch; Rodney H. Orgill; Charles Peddle; Michael F. Wiles


Archive | 1976

Pulse expanding system for microprocessor systems with slow memory

Thomas H. Bennett; Michael F. Wiles


Archive | 1974

Multiple interrupt microprocessor system

Thomas H. Bennett; Earl F. Carlow; Charles Peddle; Michael F. Wiles


Archive | 1974

Interrupt circuitry for microprocessor chip

Thomas H. Bennett; Earl F. Carlow; Rodney H. Orgill; Michael F. Wiles


Archive | 1977

Interface adaptor architecture

Thomas H. Bennett; Earl F. Carlow; Edward C. Hepworth; William D. Mensch; Charles Peddle; Gene A. Schriber; Michael F. Wiles


Archive | 1975

Interrupt system for microprocessor system

Thomas H. Bennett; Earl F. Carlow; Edward C. Hepworth; Wilbur L. Mathys; William D. Mensch; Rodney H. Orgill; Charles Peddle; Michael F. Wiles


Archive | 1975

Valid memory address enable system for a microprocessor system

Thomas H. Bennett; Earl F. Carlow; Edward C. Hepworth; Wilbur L. Mathys; William D. Mensch; Rodney H. Orgill; Charles Peddle; Michael F. Wiles


Archive | 1974

Interface adaptor having control register

Thomas H. Bennett; Earl F. Carlow; Michael F. Wiles


Archive | 1975

Master slave registers for interface adaptor

Thomas H. Bennett; Earl F. Carlow; Edward C. Hepworth; Wilbur L. Mathys; William D. Mensch; Rodney H. Orgill; Charles Peddle; Michael F. Wiles


Archive | 1976

Split low order internal address bus for microprocessor

Thomas H. Bennett

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