Thomas Hein

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques

Modern graphics subsystems (gaming PCs, midhigh end graphics cards, game consoles) have reached the 2.6-2.8 Gb/s/pin regime with GDDR3/GDDR4, and experimental work has shown per pin rates up to 6 Gb/s/pin on individual test setups. In order to satisfy the continuous demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. This paper describes a 7 Gb/s/pin 1 Gb GDDR5 DRAM and the circuit design and optimization features employed to achieve these speeds. These features include: an array architecture for fast column access, a command-FIFO designed to take advantage of special training/tracking requirements of the GDDR5 interface, a boosting transmitter to increase read eye height, sampling receivers with pre-amplification and offset control, multiple regulated internal voltage (VINT = 1.3 V) domains to control on chip power noise, and a high-speed internal VINT power generator system. The memory device was fabricated in a conventional 75 nm DRAM process and characterized for a 7 Gb/s/pin data transfer rate at 1.5 V Vext.

An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications

The graphic DRAM interface standard GDDR5X is developed as an evolutionary extension to the widely available GDDR5. The implementation presented here achieves a data rate of 12 Gb/s/pin on a single-ended signaling interface with 32 IOs for a total memory bandwidth of 48 GB/s. The GDDR5X DRAM relies on the quad data rate operation enabled by a phase-locked loop (PLL), a receiver with a pre-amplifier in a dual-regulation loop and a one-tap digital feedback equalizer (DFE). To support lower performance modes, an additional GDDR5-like operation is provided, which bypasses the PLL. The interface is realized on a conventional high-volume DRAM process to provide a cost-efficient, discrete package 8-Gb DRAM for high-performance graphic cards and compute applications.

23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applications

Over the last years, GDDR5 has emerged as the dominant standard for applications requiring high system bandwidth like graphic cards and game consoles. However, GDDR5 data rates are saturating due to limitations in the clock frequency and column-access cycle time (tCCD). To reach the data rate of 9Gb/s/pin [1], a GDDR5 DRAM has to be clocked at 2.25GHz and operate at a tCCD of 888ps. This combination makes the design of control logic, data path and memory core difficult in a typical DRAM process. Still, the industry is demanding higher system bandwidth to enable continuous improvements in the visual computing arena. For this purpose, an 8Gb GDDR5X DRAM has been developed reaching a data rate of 12Gb/s/pin, which surpasses the fastest published GDDR5 [1] by 33%. This paper introduces GDDR5X and discusses relevant circuit techniques in clock generation, receiver and transmitter design to enable the higher data rates on a conventional DRAM process.