Thomas J. Heller
IBM
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Publication
Featured researches published by Thomas J. Heller.
Ibm Journal of Research and Development | 2001
Richard E. Matick; Thomas J. Heller; Michael Ignatowski
Advances in technology have provided a continuing improvement in processor speed and capacity of attached main memory. The increasing gap between main memory and processor cycle times has required increasingly more levels of caching to prevent performance degradation. The net result is that the inherent delay of a memory hierarchy associated with any computing system is becoming the major performance-determining factor and has inspired many types of analysis methods. While an accurate performance-evaluation tool requires the use of trace-driven simulators, good approximations and significant insight can be obtained by the use of analytical models to evaluate finite cache penalties based on miss rates (or miss ratios) and queuing theory combined with empirical relations between various levels of a memory hierarchy. Such tools make it possible to readily determine trends in performance vs. changes in input parameters. This paper describes such an analysis approach--one which has been implemented in a spreadsheet and used successfully to perform early engineering tradeoffs for many uniprocessor and multiprocessor memory hierarchies.
Archive | 1996
William Todd Boyd; Thomas J. Heller; Michael Ignatowski; Richard E. Matick; Stanley E. Schuster
Archive | 1999
Michael Ignatowski; Thomas J. Heller; Gottfried Andreas Goldiran
Archive | 1997
Jeffrey H. Dreibelbis; Wayne F. Ellis; Thomas J. Heller; Michael Ignatowski; Howard Leo Kalter; David Meltzer
Archive | 2007
Thomas J. Heller
Archive | 2007
Thomas J. Heller; Hung Qui Le
Archive | 2003
Thomas J. Heller; Richard Irwin Baum; Michael Ignatowski; James Walter Rymarczyk
Archive | 2007
Thomas J. Heller; Richard L Baum
Archive | 2009
Thomas J. Heller
Archive | 2006
James Walter Rymarczyk; Michael Ignatowski; Thomas J. Heller