Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Thomas J. Heller is active.

Publication


Featured researches published by Thomas J. Heller.


Ibm Journal of Research and Development | 2001

Analytical analysis of finite cache penalty and cycles per instruction of a multiprocessor memory hierarchy using miss rates and queuing theory

Richard E. Matick; Thomas J. Heller; Michael Ignatowski

Advances in technology have provided a continuing improvement in processor speed and capacity of attached main memory. The increasing gap between main memory and processor cycle times has required increasingly more levels of caching to prevent performance degradation. The net result is that the inherent delay of a memory hierarchy associated with any computing system is becoming the major performance-determining factor and has inspired many types of analysis methods. While an accurate performance-evaluation tool requires the use of trace-driven simulators, good approximations and significant insight can be obtained by the use of analytical models to evaluate finite cache penalties based on miss rates (or miss ratios) and queuing theory combined with empirical relations between various levels of a memory hierarchy. Such tools make it possible to readily determine trends in performance vs. changes in input parameters. This paper describes such an analysis approach--one which has been implemented in a spreadsheet and used successfully to perform early engineering tradeoffs for many uniprocessor and multiprocessor memory hierarchies.


Archive | 1996

Integrated processing and L2 DRAM cache

William Todd Boyd; Thomas J. Heller; Michael Ignatowski; Richard E. Matick; Stanley E. Schuster


Archive | 1999

Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls

Michael Ignatowski; Thomas J. Heller; Gottfried Andreas Goldiran


Archive | 1997

Multi-port multiple-simultaneous-access DRAM chip

Jeffrey H. Dreibelbis; Wayne F. Ellis; Thomas J. Heller; Michael Ignatowski; Howard Leo Kalter; David Meltzer


Archive | 2007

Computing System with Transactional Memory Using Millicode Assists

Thomas J. Heller


Archive | 2007

Transactional memory system which employs thread assists using address history tables

Thomas J. Heller; Hung Qui Le


Archive | 2003

Multiprocessor system with dynamic cache coherency regions

Thomas J. Heller; Richard Irwin Baum; Michael Ignatowski; James Walter Rymarczyk


Archive | 2007

Transactional Memory Computing System with Support for Chained Transactions

Thomas J. Heller; Richard L Baum


Archive | 2009

Hybrid Transactional Memory System (HybridTM) and Method

Thomas J. Heller


Archive | 2006

Multiple-core processor supporting multiple instruction set architectures

James Walter Rymarczyk; Michael Ignatowski; Thomas J. Heller

Researchain Logo
Decentralizing Knowledge