Thomas Leneke
Otto-von-Guericke University Magdeburg
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Thomas Leneke.
Circuit World | 2009
Thomas Leneke; Soeren Hirsch; Bertram Schmidt
Purpose – The purpose of this paper is to present a new multilayer process for three‐dimensional molded interconnect devices (3D‐MIDs) that allows the assembly of modern area array packaged semiconductors.Design/methodology/approach – A new 3D‐MID multilayer process based on local overmolding is developed. To investigate this new process, a 3D demonstrator is designed, simulated and fabricated. Various technologies such as injection molding, maskless laser assisted electroless metallization, overmolding and laser via drilling are used.Findings – Using the new 3D‐MID multilayer process a 3D demonstrator with three metallization layers is fabricated. Injection molding simulation is utilized to ensure a feasible demonstrator design. It is shown that a surface laser treatment improves layer‐to‐layer adhesion during the process. Shear and pull tests prove the adhesion promotion. The 3D fine‐pitch‐metallization is done down to 60 μm track width. Via resistance is measured by four terminal sensing in agreement w...
electronics system-integration technology conference | 2008
Thomas Leneke; Soeren Hirsch; Bertram Schmidt
The miniaturization of overall systems plays a key role for the propagation of technological applications. To meet future requirements in size decreasing environments especially the packaging and mounting of silicon devices needs new impulses. 3D-MIDs (3-dimensional molded interconnect devices) exhibit a high potential for smart packages and assemblies. The integration of various functionalities (electrical connections, housing, thermal management, mechanical support) in one 3-dimensional shaped circuit carrier makes a further system shrinking possible. The compatibility between 3D-MIDs and high density fine-pitch semiconductor packages (like BGAs, MCMs, CSPs or even bare dies) is limited. Due to lack of a 3-dimensional multilayer technology the wiring of semiconductors with a high I/O count is critical. Therefore a new 3D-MID multilayer process is developed and combined with an established 3D-MID metallization process. The new multilayer process is investigated with respect to its electrical and mechanical behavior. A demonstrator was fabricated to perform desired tests.
2012 4th Electronic System-Integration Technology Conference | 2012
Marc-Peter Schmidt; Thomas Leneke; Soeren Hirsch; Bertram Schmidt
The implementation of fluidic functions in 3D-MID (three dimensional molded interconnect devices) allows to create a new field of applications and enhanced system solutions. We report about the capabilities of MID for the packaging of chip modules with microfluidic functions. A mechanically stable and leak tight fluidic connection is needed between the microfluidic chip and the environment. For this purpose a fluidic interposer is fabricated by the LDS-process (laser direct structuring) and includes a metallization for electrical signals and channel structures for fluidic features. The presented interposer enables the transformation of fluidic ports from the macro- to the micro scale. To characterize the device, a microfluidic test chip made of silicon and glass (Borofloat®) has been fabricated and mounted on the fluidic interposer by a flip-chip vapor phase process. Finally the potential of the system is shown by testing maximum pressurization and fluidic sealing.
electronics system integration technology conference | 2010
Andreas Brose; Thomas Leneke; Soeren Hirsch; Bertram Schmidt
The permanent miniaturization of automotive, medical and consumer products requires alternative packaging solutions. So far most electronic products are circuit boards mounted in a separate body. An upcoming alternative are moulded interconnect devices (3D-MID). They combine the substrate function for interconnects and the housing function. To ensure a high integration density it is necessary to apply fine pitch metallizations to the polymer devices.
international conference on electronics packaging | 2014
Thomas Leneke; Sören Majcherek; Soeren Hirsch; Marc-Peter Schmidt; Bertram Schmidt
Three dimensional molded interconnect devices (MID) with fluidic features offer new possibilities for the packaging of microfluidic components. This paper reports about an MID based fluidic interposer to bridge the micro-macro gap of fluid delivery in microfluidic systems. The interposer is fabricated by standard MID fabrication technology and includes a metallization for electrical signals and channel structures for fluidic functions. A microfluidic test chip is assembled to the interposer by a flip-chip process. The proposed interposer is suitable for pressure and capillary driven flows. Results from pressurization testing with liquids and gases are given.
Volume 13: Nano-Manufacturing Technology; and Micro and Nano Systems, Parts A and B | 2008
Thomas Leneke; Soeren Hirsch; Bertram Schmidt
A key factor for the propagation of technological applications is the miniaturization of respective components, subsystems and overall systems. To meet future requirements in such size decreasing environments the packaging and mounting technology needs new impulses. 3D-MIDs (three-dimensional molded interconnect devices) exhibit a high potential for smart packages and assemblies. A three-dimensional shaped circuit carrier allows the integration of various functional features (e.g. electrical connections, housing, thermal management, mechanical support). This combination makes a further system shrinking possible. Yet, the mounting of high-density area-array fine-pitch packaged semiconductors (BGA, CSP, MCM) or bare dies to 3D-MIDs is problematic. The lack of a three-dimensional multilayer technology makes a collision free escape routing for devices with a high I/O count difficult. Therefore a new 3D-MID multilayer process was developed and combined with an established 3D-MID metallization process. A demonstrator with three metallization layers, capable, e.g., for flip-chip mounting of area-array packages, is fabricated. The multilayer structure of the demonstrator is investigated with respect to the mechanical and electrical behavior.© 2008 ASME
Microsystem Technologies-micro-and Nanosystems-information Storage and Processing Systems | 2008
Soeren Majcherek; Thomas Leneke; Soeren Hirsch
Archive | 2011
Thomas Leneke; Bertram Schmidt; Sören Hirsch
Transactions of The Japan Institute of Electronics Packaging | 2009
Thomas Leneke; Soeren Hirsch
Archive | 2009
Sören Hirsch; Dirk Kaden; Thomas Leneke; Bertram Schmidt