Thomas Martin Wicki

The Mercury Interconnect Architecture: a cost-effective infrastructure for high-performance servers

This paper presents HALs Mercury Interconnect Architecture, an interconnect infrastructure designed to link commodity microprocessors, memory, and I/O components into high-performance multiprocessing servers. Both shared-memory and message-passing systems, as well as hybrid systems are supported by the interconnect. The key attributes of the Mercury Interconnect Architecture are: low latency, high bandwidth, a modular and flexible design, reliability/availability/serviceability (RAS) features, and a simplicity that enables very cost-effective implementations. The first implementation of the architecture links multiple 4-processor Pentium™ Pro based nodes. In a 4-node (16-processor) shared-memory configuration, this system achieves a remote read latency of just over 1 µs, and a maximum interconnect bandwidth of 6.4 GByte/s. Both of these parameters far outpace comparable SCI-based solutions, while utilizing much fewer hardware components.

A 285 MHz 6-port plesiochronous router chip with non-blocking cross-bar switch

The HAL router chip is a 285 MHz 6-port plesiochronous packet-switched routing chip with non-blocking cross-bar switch. It combines very high bandwidth (4.5 GByte/s per port, 27 GByte/s total raw bandwidth), low fall-through latency (32 ns), no internal blocking, three arbitration priorities with in-order delivery, a flexible source routing scheme, virtual-cut-through routing, and robust reverse flow control.

A 9.6 GigaByte/s throughput plesiochronous routing chip

The design of a very high performance routing chip with six bi-directional link ports and an aggregate sustained throughput of 9.6 GByte/s is described The routing chips will form the switching fabric of a cache-coherent, Non-Uniform Memory Access (cc-NUMA) multiprocessor system. The key elements of the chip are a non-blocking internal crossbar; synchronization circuits for plesiochronous operation (i.e. no central system clock required) and reliance on hardware end-to-end error checking. The chip has recently been taped out.