Thomas Ortlepp

Three-dimensional multi-terminal superconductive integrated circuit inductance extraction

Accurate inductance calculations are critical for the design of both digital and analogue superconductive integrated circuits, and three-dimensional calculations are gaining importance with the advent of inductive biasing, inductive coupling and sky plane shielding for RSFQ cells. InductEx, an extraction programme based on the three-dimensional calculation software FastHenry, was proposed earlier. InductEx uses segmentation techniques designed to accurately model the geometries of superconductive integrated circuit structures. Inductance extraction for complex multi-terminal three-dimensional structures from current distributions calculated by FastHenry is discussed. Results for both a reflection plane modelling an infinite ground plane and a finite segmented ground plane that allows inductive elements to extend over holes in the ground plane are shown. Several SQUIDs were designed for and fabricated with IPHTs 1 kA cm − 2 RSFQ1D niobium process. These SQUIDs implement a number of loop structures that span different layers, include vias, inductively coupled control lines and ground plane holes. We measured the loop inductance of these SQUIDs and show how the results are used to calibrate the layer parameters in InductEx and verify the extraction accuracy. We also show that, with proper modelling, FastHenry can be fast enough to be used for the extraction of typical RSFQ cell inductances.

Demonstration of digital readout circuit for superconducting nanowire single photon detector.

We demonstrate the transfer of single photon triggered electrical pulses from a superconducting nanowire single photon detector (SNSPD) to a single flux quantum (SFQ) pulse. We describe design and test of a digital SFQ based SNSPD readout circuit and demonstrate its correct operation. Both circuits (SNSPD and SFQ) operate under the same cryogenic conditions and are directly connected by wire bonds. A future integration of the present multi-chip configuration seems feasible because both fabrication process and materials are very similar. In contrast to commonly used semiconductor amplifiers, SFQ circuits combine very low power dissipation (a few microwatts) with very high operation speed, thus enabling count-rates of several gigahertz. The SFQ interface circuit simplifies the SNSPD readout and enables large numbers of detectors for future compact multi-pixel systems with single photon counting resolution. The demonstrated circuit has great potential for scaling the present interface solution to 1,000 detectors by using a single SFQ chip.

Reduced Power Consumption in Superconducting Electronics

Rapid single flux quantum (RSFQ) electronics is based on the Josephson junction as an active switching element. In standard RSFQ circuits its switching energy is much lower than the static power consumption caused by the resistive current distribution network. Due to this thermal heating of the chip, the maximum number of junctions on a single chip is limited to about 1 million. The frequency-dependent contribution to power dissipation from junction switchings is only about 2 percent of the static one. This fact limits the direct construction of VLSI systems for high-performance computing as well as small-scale circuit applications in the vicinity of ultra-sensitive detectors or even quantum circuits. We present an assessment of different approaches for reducing the static power consumption by investigating the potential of inductive bias distribution networks as well as reduced critical currents. We analyse the operation stability of simple digital circuits with 5 times smaller critical currents at 4.2 K. The combination of the reduced critical currents and inductive biasing can provide digital superconductive circuits with significantly reduced static power consumption.

64-kb Hybrid Josephson-CMOS 4 Kelvin RAM With 400 ps Access Time and 12 mW Read Power

We have designed, simulated, fabricated, and tested a 64-kb hybrid Josephson-CMOS memory using a 5 mm × 5 mm Josephson interface chip and a 2.0 × 1.5 mm CMOS chip. The Josephson chip uses the Hypres 4.5 kA/cm2 niobium technology and the CMOS chip is made using the TSMC 65-nm technology. The chips are connected using short wire bonds in a piggy-back package. The chip sizes and pad layouts have been constrained to allow testing in our wideband American Cryoprobe Model BCP-2 test probe to measure ultrashort delays. The test signals of 5-mV amplitude are chosen to represent the signals that would be supplied to the memory in a digital computing or signal processing system. Each input signal is first amplified in a four-junction logic gate driving a Suzuki stack, which, in turn, drives a highly sensitive CMOS comparator that raises the signal to volt level. Such amplifiers are provided for the address, data, read, and write inputs to the CMOS memory. Output currents from the memory cells are detected by ultrafast four-junction logic gates providing 5-mV output signals; an equivalent arrangement was used for the delay tests. The overall read delay is the access time, which we find to be about 400 ps. We extrapolate from the measured and calculated power dissipation in this partially accessed 64-kb memory to a fully accessed 64-kb memory and find the expected overall read power dissipation to be about 12 mW for operation at 1 GHz.

Orthogonal sequencing multiplexer for superconducting nanowire single-photon detectors with RSFQ electronics readout circuit

We propose an efficient multiplexing technique for superconducting nanowire single-photon detectors based on an orthogonal detector bias switching method enabling the extraction of the average count rate of a set of detectors by one readout line. We implemented a system prototype where the SNSPDs are connected to an integrated cryogenic readout and a pulse merger system based on rapid single flux quantum (RSFQ) electronics. We discuss the general scalability of this concept, analyze the environmental requirements which define the resolvability and the accuracy and demonstrate the feasibility of this approach with experimental results for a SNSPD array with four pixels.

RSFQ electronics for controlling superconducting polarity switches

Superconducting radiation sensors are of particular interest for imaging applications in the sub-mm wavelength band because of their extraordinary sensitivity. The rising number of sensors integrated in one array entails the requirement of multiplexing techniques in order to reduce the number of wires leading into the cryogenic stage and thus reduce the thermal losses. One kind of promising code division multiplexing technique is based on a current steering switch (CSS), which is composed of two identical superconducting quantum interference devices (SQUIDs) in parallel current paths. One of them is switched from the superconducting into the normal state controlled by the applied magnetic flux. In this way the signal path can be altered and they can act as a polarity switch for analogue signals. We pursue this concept to use rapid single flux quantum (RSFQ) electronics for controlling these switches. As a first step, the SQUIDs of the CSS are inductively coupled to the storing loops of two delay flip flops (DFFs). Thus, one is able to toggle the polarity of the analogue switch by controlling the state of the DFF by RSFQ control signals. The results of simulations and measurements and also margin analyses are discussed.

High-Speed Hybrid Superconductor-to-Semiconductor Interface Circuit With Ultra-Low Power Consumption

Superconductor electronics for high-performance computing and high-speed analog-to-digital converters requires multi-channel digital data links. Most difficult is the amplification of the weak signals from the superconductor circuit to the volt level of semiconductor electronics. We developed a hybrid digital interface based on a Josephson latching driver, the so-called Suzuki stack, and a clocked CMOS comparator. The input can be directly triggered by a single flux quantum pulse and the output provides a 1 V CMOS-level signal. In contrast to existing systems, our interface is optimized for ultra-low-power consumption to enable its application for parallel multi-bit data interfaces. We provide evaluation of various types of Suzuki stacks and various CMOS comparators. We present experimental data on the delay of the overall hybrid interface and the total power consumption. The bit-error rate has been measured to be below 10-12. We will discuss the trade-off among circuit robustness, speed, and power consumption.

Linearity of a Digital SQUID Magnetometer

A digital SQUID magnetometer measures the magnetic field amplitude by counting integer magnetic flux quanta within its superconducting input loop. Although resolution is limited in comparison to analog SQUID systems, the digital SQUID is able to outrange its analog counterpart with regard to parameters such as slew rate and dynamic range. In this work we evaluate the performance of a digital SQUID based on a three-level logic. Due to this basic principle, we face a combination of two comparator grayzones leading to hysteretic behavior of the sensor that produces a “dead zone” in the signal reversal point. The dependence of the comparator threshold on design parameters is investigated by simulation studies and reconfirmed by experimental results. We were able to reach a total dynamic range of more than 540,000 flux quanta (about 19 bit) with a linearity error of about 5 bit due to the mentioned hysteretic behavior. We discuss the results of our investigations and provide guidelines to extend dynamic range and linearity for future sensor designs.

Optimization of a digital SQUID magnetometer in terms of noise and distortion

The digital SQUID magnetometer takes advantage of flux quantization in a superconducting loop in order to measure magnetic fields. The core element of the digital SQUID is a Josephson comparator with a superconducting antenna loop attached to one of its junctions. Evaluation of the circuit from the system?s point of view requires an analysis in the frequency domain. In order to obtain a high-resolution fast Fourier transform, large datasets are necessary which are difficult to generate with transient simulation tools. In this work we derive a behavioural model for the digital SQUID in order to overcome restrictions imposed by transient simulation. By means of this model the influence of the comparator grey zone and the input loop inductance on the system performance was analysed. In order to assess the system, evaluation criteria based on the power spectral density were applied, which are commonly used for characterization of semiconductor analogue to digital converters. As a result of this study, design guidelines for an optimum antenna inductance depending on the comparator grey zone are derived, allowing us to achieve an optimum system performance in terms of noise and distortion.

Design guidelines for Suzuki stacks as reliable high-speed Josephson voltage drivers

The application of superconducting circuits for high-performance computing and high-speed analog-to-digital converters suffers from the difficulty of amplifying the weak signals of superconducting circuits to the volt level of semiconductor electronics. We refer to the most accepted Josephson circuit used to amplify weak signals of about a millivolt to several tens of millivolts as a Suzuki stack. It can be directly triggered by a single flux quantum pulse and has a very high switching speed of about 25 ps. We report here an in-depth study of design issues for Suzuki stacks with extensive systematic simulations as well as experimental results. We explain the origin of previously reported phenomena such as multiple-level switching, high bit-error-rates, and interactions between stacks, and give design guidance for avoidance of such problems. We show experimental results for a set of Suzuki stacks operating correctly and independently with a single power supply. The presented design guidelines address important characteristics that need to be optimized: output voltage, bias margins, operating frequency, bit-error-rate, delay, power dissipation, and physical size. (Some figures may appear in colour only in the online journal)