Thomas S. Anantharaman

Singular extensions: adding selectivity to brute-force searching

Abstract Brute-force alpha-beta search of games trees has proven relatively effective in numerous domains. In order to further improve performance, many brute-force game-playing programs have used the technique of selective deepening, searching more deeply on lines of play identified as important. Typically these extensions are based on static, domain-dependent knowledge. This paper describes a modification of brute-force search, singular extensions, that allows extensions to be identified in a dynamic, domain-independent, low-overhead manner. Singular extensions, when implemented in a chess-playing program, resulted in significant performance improvements.

A hardware accelerator for speech recognition algorithms

This paper describes two custom architectures tailored to a speech recognition beam search algorithm. Both architectures have been simulated using real data and the results of the simulation are presented. The paper also describes the design process of the custom architectures and presents a number of ideas on the automatic design of custom systems for data dependent computations.

BEAM. An accelerator for speech recognition

BEAM is a hardware accelerator that has been designed and built for real-time execution of the SPHINX speaker-independent, continuous-speech recognition system and similar systems. SPHINX on BEAM is able to recognize sentences from a 1000-word vocabulary and a perplexity-60 grammar in about 1.3 times real time. BEAM does not use any custom integrated circuits. The architecture of the accelerator is described. Performance data are given and compared with those for other architectures. It is concluded that BEAM demonstrates how general-purpose technology can be used to build systems that are substantially faster than general-purpose systems.<<ETX>>

Compiling path expressions into VLSI circuits

Path expressions were originally proposed by Campbell and Habermann [2] as a mechanism for process synchronization at the monitor level in software. Not surprisingly, they also provide a useful notation for specifying the behavior of asynchronous circuits. Motivated by these potential applications we investigate how to directly translate path expressions into hardware. Our implementation is complicated in the case of multiple path expressions by the need for synchronization on event names that are common to more than one path. Moreover, since events are inherently asynchronous in our model, all of our circuits must be self-timed. Nevertheless, the circuits produced by our construction have are proportional to N · log(N) where N is the total length of the multiple path expression under consideration. This bound holds regardless of the number of individual paths or the degree of synchronization between paths. Furthermore, if the structure of the path expression allows partitioning, the circuit can be laid out in a distributed fashion without additional area overhead.

A family of custom VLSI circuits for speech recognition

The design of a custom VLSI circuit that has the potential of achieving a high throughput when executing one of the most computationally expensive modules of a speech recognition system is presented. The architecture of the device is described in terms, of a set of self-timed building blocks that implement arithmetic operations, storage and input/output functions. The formalism used to describe the architecture makes it easy to define variations of the basic structure in order to deal with recognition systems that use different heuristics and search different kinds of databases. A tool that helps the designer investigate the area/speed trade-offs is also described.

Custom data-flow machines for speech recognition

The goal of the paper is to present some of the design characteristics and performance of a special purpose custom machine that has the potential of improving the speed of the implementation of a beam search algorithm by two orders of magnitude when compared with a general purpose architecture implementation. The paper also describes the architecture of a general purpose self-timed device that can be used in implementing such a machine.