Thomas S. Murray

Design of a CMOS A2I data converter: Theory, architecture and implementation

We present the design of an analog-to-information (A2I) converter consisting of parallel analog processing channels, whose output is sampled by traditional analog-to-digital converters (ADCs). The architecture employs a reconfigurable analog front-end that modulates the signal of interest with a high-speed digital chipping sequence and integrates the result prior to sampling at a low rate. This front-end is combined with a digital controller which generates the chipping sequences and processes the digitized samples. The result is a highly versatile architecture that is mapped efficiently on a single CMOS chip.

Evaluating on-chip interconnects for low operating frequency silicon neuron arrays

We present a quantitative analysis of the limits of the time-multiplexed Address Event Representation (AER) bus for on-chip connectivity of silicon neuron arrays. In particular, we evaluate its potential to support high density and low power neural arrays operating in the subthreshold regime. Our analysis shows that due to low clock frequencies when operating in the subthreshold regime, the traditional single AER bus does not scale to large neural arrays. We find that a switched mesh network improves scalability, however, a crosspoint architecture overcomes the bandwidth limitations altogether. By trading off area for improved performance, it increases the number of neurons that can be supported in a single chip neural array.

The Johns Hopkins University multimodal dataset for human action recognition

The Johns Hopkins University MultiModal Action (JHUMMA) dataset contains a set of twenty-one actions recorded with four sensor systems in three different modalities. The data was collected with a data acquisition system that includes three independent active sonar devices at three different frequencies and a Microsoft Kinect sensor that provides both RGB and Depth data. We have developed algorithms for human action recognition from active acoustics and provide benchmark baseline recognition performance results.

Signal to symbol converters: Overview, opportunities and challenges

Signal to symbol converters (SSCs) are an emerging class of integrated microsystems aimed at an informed and intelligent conversion of signals to symbols. We present an architecture overview for signal to symbol converters, discuss related prior work and outline future opportunities and challenges.

Action recognition using micro-Doppler signatures and a recurrent neural network

This paper explores the long short-term memory (LSTM) recurrent neural network for human action recognition from micro-Doppler signatures. The recurrent neural network model is evaluated using the Johns Hopkins MultiModal Action (JHUMMA) dataset. In testing we use only the active acoustic micro-Doppler signatures. We compare classification performed using hidden Markov model (HMM) systems trained on both micro-Doppler sensor and Kinect data with LSTM classification trained only on the micro-Doppler signatures. For HMM systems we evaluate the performance of product of expert based systems and systems trained on concatenated sensor data. By testing with leave one user out (LOUO) cross-validation we verify the ability of these systems to generalize to new users. We find that LSTM systems trained only on micro-Doppler signatures outperform the other models evaluated.

Bio-inspired system architecture for energy efficient, BIGDATA computing with application to wide area motion imagery

In this paper we discuss a brain-inspired system architecture for real-time big velocity BIGDATA processing that originates in large format tiled imaging arrays used in wide area motion imagery ubiquitous surveillance. High performance and high throughput is achieved through approximate computing and fixed point arithmetic in a variable precision (6 bits to 18 bits) architecture. The architecture implements a variety of processing algorithms classes ranging from convolutional networks (Con-vNets) to linear and non-linear morphological processing, probabilistic inference using exact and approximate Bayesian methods and ConvNet based classification. The processing pipeline is implemented entirely using event based neuromorphic and stochastic computational primitives. The system is capable of processing in real-time 160 × 120 raw pixel data running on a reconfigurable computing platform (5 Xilinx Kintex-7 FPGAs). The reconfigurable computing implementation was developed to emulate the computational structures for a 3D System on Chip (3D-SOC) that will be fabricated in the 55nm CMOS technology and it has a dual goal: (i) algorithm exploration and (ii) architecture exploration.