Thomas Schwederski

Static synchronization beyond VLIW

A key advantage of SIMD (Single Instruction stream, Multiple Data stream) architectures is that synchronization is effected statically at compile-time, hence the execution-time cost of synchronization between “processes” is essentially zero. VLIW (Very Long Instruction Word) machines are successful in large part because they preserve this property while providing more flexibility in terms of what kinds of operations can be parallelized. In this paper, we propose a new kind of architecture — the “static barrier MIMD” or SBM — which can be viewed as a further generalization of the parallel execution abilities of static synchronization machines. Barrier MIMDs are asynchronous Multiple Instruction stream Multiple Data stream architectures capable of parallel execution of loops, subprogram calls, and variable-execution-time instructions. However, instead of using barriers as a synchronization mechanism, the proposed barrier hardware is used to impose static timing constraints. Since the compiler can know at compile time all instructions which each processor could be executing when a particular conceptual synchronization operation is needed, it can resolve most synchronizations by using VLIW-like compile-time instruction scheduling — without use of a runtime synchronization mechanism. The effect is that the proposed barrier mechanism greatly extends the generality of efficient static scheduling without adding a significant hardware cost. Traditional, directed-synchronization, MIMD architectures are more flexible than barrier MIMDs, but the benefits of static scheduling make barrier MIMDs superior for fine to medium grain parallelism. Both the barrier architecture and the supporting compiler technology are discussed in this paper.

On scan path design for stuck-open and delay fault detection

A novel scan path design technique is presented, which facilitates the application of two-pattern tests by transition shifting. The scan path is composed based on the test data set as a graph matching problem. For the reduction of the required test application time, a novel reconfigurable scan path architecture is presented, which is synthesized based on the test data set. This reconfigurable scan path concept is applicable not only to two-pattern test sets but also when the test program has been generated for stuck-at faults.<<ETX>>

PASM: a reconfigurable parallel system for image processing

PASM is a multifunction partitionable SIMD/MIMD system being designed at Purdue for parallel image understanding. It is to be a large-scale, dynamically reconfigurable multimicroprocessor system, which will incorporate over 1,000 complex processing elements. Parallel algorithm studies and simulations have been used to analyze application tasks in order to guide design decisions. A prototype of PASM is under construction (funded by an equipment grant from IBM), including 30 Motorola MC68010 processors, a multistage interconnection network, five disk drives, and connections to the Purdue Engineering Computer Network (for access to peripherals, terminals, software development tools, etc.). PASM is to serve as a vehicle for studying the use of parallelism for performing the numeric and symbolic processing needed for tasks such as computer vision. The PASM design concepts and prototype are overviewed and brief examples of parallel algorithms are given.

Efficient masking techniques for large-scale SIMD architectures

SIMD (single-instruction-stream, multiple-data-stream) architectures require mechanisms that efficiently enable and disable mask processors to support flexible programming. Most current SIMD architectures use local masking. Global processor masks, specified by the control unit, are more efficient for tasks where the masking is data independent. An efficient hybrid masking technique that supports global masking, as well as local masking, for SIMD architectures constructed from standard microprocessors is proposed. A design for the hybrid mechanism is described, and its experimental performance using the existing PASM prototype is examined. It is shown that the hybrid masking technique can increase the utilization of PEs and thus increase performance, the degree of improvement being algorithm dependent.<<ETX>>

A model of task migration in partitionable parallel processing systems

The effects of task migration (i.e. movement of a task from one partition to another) in systems with multistage cube or hypercube networks are studied. Direct overhead encompasses the cost of moving the task when no other tasks affect the migration, while indirect overhead is the additional time needed for migration that is due to influences of other tasks. The sum of direct and indirect overhead is the time needed to migrate a task. In addition, the migration can affect other tasks, and thus can incur a migration penalty. The indirect overhead and migration penalty represent the interference that can occur in the interconnection network between the migrating task and other tasks attempting to use the network simultaneously. A model for parameterizing migration costs is given. This research is part of the PASM parallel-processing project.<<ETX>>

On structured gate forest VLSI design

Abstract The opportunities for structured VLSI design on a Sea-of-Gates template are discussed. From a critique on the use of standard cells, the Gate Forest approach for testable module compilation is introduced. With suitable tooling architectured in an open CAD environment, this allows for almost Full Custom layout efficiency.

CAPS: a coding aid for PASM

Programming parallel machines is very difficult. First, generating an algorithm requires the programmer to assimilate the interactions of multiple threads of control. Second, synchronization and communication among the threads must be addressed to avoid contention and deadlock. Then, once the program is executing on the parallel system and does not function correctly or performs poorly, the debugging of multiple threads is a complicated problem [21]. Additionally, debugging software is an activity that requires systematic attention to detail. Success is a function of the experienced individual involved and the tools employed. The ability to efficiently debug software requires the wisdom to know what questions to ask, the ability to analyze the answers received, and the knowledge to formulate the best next question. To aid in this interactive process, the programmer needs information about the run-time behavior of the program.

Large-scale parallel processing systems

Abstract Parallel processing is an area of growing interest to the computer science and engineering communities. This paper is an introduction to some of the concepts involved in the design and use of large-scale parallel systems. Parallel machines that are classified as SIMD (synchronous) and MIMD (asynchronous) systems, composed of a large number of microprocessors, are explored. Parallel algorithms are examined, using image smoothing, recursive doubling and contour tracing as examples. Single stage and multistage networks are discussed. The single stage Cube, PM21, Four Nearest Neighbor and Shuffle-Exchange networks are presented, and the multistage Cube network is described. Case studies of three microprocessor-based systems are given as examples of parallel machine designs, specifically the MPP SIMD machine, the Ultracomputer MIMD system, and the PASM SIMD/MIMD machine.

Strategies for the Massively Parallel Simulation of Interconnection Networks

Methods for enhancing multistage interconnection network simulators running on massively parallel SIMD computers are presented. Aspects of parallel simulation of interconnection networks are discussed and different strategies of mapping the architecture of the network to be simulated onto the parallel machine are studied and compared. As case studies, two strategies of mapping synchronous multistage cube networks onto the MasPar MP-1 SIMD machine are explored and their implementations are compared. The methods result in an efficient simulator which can process 10^9 data packets in 40 minutes.