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Dive into the research topics where Thomas V Spencer is active.

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Featured researches published by Thomas V Spencer.


Proceedings of COMPCON '94 | 1994

A workstation I/O system on a chip

Thomas V Spencer; Frank John Lettang; Curtis R. McAllister; Tony Riccio; Joe Orth; Don Weiss; Brian K. Arnold

Describes the I/O sub-system for the new low-end of HPs Series 700 family of workstations. The paper focuses on the single piece of custom VLSI that serves as the heart of the I/O sub-system. This chip was optimized to minimize the manufacturing cost of the system while maintaining functional compatibility and comparable performance with existing members of the Series 700 family. A wide range of functionalities from a variety of sources (including outside vendors) was combined on a single piece of silicon to obtain an optimal balance between manufacturing cost, performance, and software compatibility.<<ETX>>


Archive | 2002

System and method for managing data in an I/O cache

Thomas V Spencer; Robert J. Horning


Archive | 2001

System and method for managing data in an asynchronous I/O cache memory to maintain a predetermined amount of storage space that is readily available

Thomas V Spencer


Archive | 1998

Bus bridge and method for ordering read and write operations in a write posting system

Derek Alan Sherlock; Thomas V Spencer; Francisco Corella


Archive | 1999

System and method for managing data in an asynchronous I/O cache memory

Thomas V Spencer; Robert J. Horning


Archive | 2001

System for bridging a system bus with multiple PCI buses

Thomas V Spencer


Archive | 1998

Method and apparatus for ensuring data consistency between an i/o channel and a processor

William R. Bryg; Monish S. Shah; Thomas V Spencer


Archive | 1997

Main memory buffer for low cost / high performance input/output of data in a computer system

Thomas V Spencer


Archive | 1998

System and method for performing memory fetches for an ATM card

Thomas V Spencer; Robert J. Horning; Monish S. Shah


Archive | 1998

Asynchronous input/output cache having reduced latency

Thomas V Spencer; Monish S. Shah

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