Tian Song

A High-Performance URL Lookup Engine for URL Filtering Systems

URL filtering systems provide a simple and effective way to prevent people from browsing undesirable or malicious websites. These systems require a well-designed URL lookup method as the core operation. A high-performance URL lookup engine is proposed in this paper for URL filtering systems. It combines a URL compression algorithm with a multiple string matching based (Wu-Manber-like) matching algorithm. Using this method, the proposed URL lookup engine can achieve high URL lookup performance and efficient memory utilization for storing the ever-increasing URL blacklist with the ability of prefix matching. Experiments with actual URL blacklists and requested URL sets show that our engine can save about 80% memory usage for storing URL blacklists, and reduce 58%-162% URL lookup time compared with the state-of-the-art URL lookup methods.

Energy evaluation of gigabit routers towards energy efficient network

Energy efficient routers are a promising step forward in the road-map towards energy efficient networking. In this paper, we use gigabit routers to measure and evaluate the impacts of green technologies in different scenarios. These programmable NetFPGA based routers come with the inbuilt feature of frequency scaling which can reduce the operational frequency of the board by half from 125MHz to 62.5MHz. Router power consumption is compared for standard and low frequency modes with different numbers of activated ports. Perpacket and per-byte energy costs in different cases with different packet sizes are measured and analyzed to evaluate the effects of frequency adjustment. Finally, a simple energy model for real traffic is proposed and evaluated. This paper reveals the internal power usage of a gigabit router at the granularity of packet, and header and payload byte level, and offers the reader a clear understanding of the potential power savings at different operational router frequencies, for different numbers of activated ports, various traffic loads and packet sizes, which would assist the green data center networks.

RocketTC: A high throughput traffic classification architecture

Real-time traffic classification is becoming increasingly critical for network management, traffic engineering, and network security. Current software-based solutions, however, have difficulties dealing with a great number of flows in todays high-speed networks. This paper proposes RocketTC, a scalable FPGA-based architecture, to accelerate traffic classification while maintaining high accuracy. It combines two significant elements: (1) an efficient flow management scheme using on-chip BRAMs for storing the flow table, and (2) a parallel and pipelined classification engine array with partial dynamic reconfiguration (PDR) on FPGA. We have implemented and evaluated RocketTC on Xilinx Virtex-5 FPGA based platform. Our results show a sustained throughput of over 20 Gbps for minimum packet size of 40 bytes, and high accuracy above 97% for classifying nearly a hundred popular applications. Additionally, it is easy for RocketTC to update more application types.

A multiple simple regular expression matching architecture and coprocessor for deep packet inspection

Pattern matching and regular expression matching are all the critical components for content inspection based applications. But current regular expression matching algorithms or architecture cannot provide a perfect solution for whole matching problem. In some real network security applications, exact strings are the biggest part of rule set, and the second part is simple regular expressions (dot-star and AND-logic), and the other complex regular expressions only occupy a very small part. So, we propose a new hardware-based multiple simple regular expression matching architecture, called MSRM, for Dot-Star and AND-logic regular expressions. Firstly, software compiler splits simple regular expressions into exact strings and relations. Multi-string-matching module judges whether strings match and outputs the matched ID. Based on these matched information and pre-generated RAM data, MSRM can judge whether dot-star and AND-logic regular expressions are satisfied easily and quickly. Experiments with random test data and ClamAV rule set show that MSRM can achieve a high throughput of 2.1 and 2.8 Gbps using Virtex2 and Virtex4 devices respectively which is much higher than software algorithms.

Dynamic frequency scaling architecture for energy efficient router

Recently, energy expenditures of the Internet have increased dramatically, raising energy issue of routers an urgent problem in relative research areas. In fact, much device surplus and redundancy are introduced during network planning for rarely appeared traffic peak hours and device failures, wasting energy most of the time. In this work, an energy-aware architecture is proposed for routers, which could trade system performance for energy savings while traffic is low by scaling frequencies of its inner components. We also explore multi-frequency modulation strategies to optimize the energy saving effect. The result shows that our prototype router could save about 40% of its peak power consumption.

Fine-grained power scaling algorithms for energy efficient routers

Energy efficient router is one of the most important and promising devices in the roadmap towards green communication and networking. In recent years, automatical power scaling adapting with real-time network traffic in a router has been proved to be practical on real hardware, which is an implementation under the traffic aware philosophy. In this paper, we further explore this direction, and present four real-time power scaling algorithms for the fine-grained energy management within a router. These algorithms are all based on the traffic aware philosophy. We first classify the traffic characteristics into three categories of the core router, access router and home router and analyze the differences among them. Then, we propose two design methodologies, periodical scaling and threshold scaling, and address four algorithms in details. Finally, we use real network traffic to evaluate these algorithms and draw the conclusions. The experiments on real traffic show that more than 40% of the energy in a router can be saved by using proposed system-level power scaling methods. Based on those evaluations, we also find that three status modes with two working frequencies and a sleep in a router are enough to achieve near-optimal energy efficiency by using our algorithms, which indicates an easy and practical hardware modification.

EABF: Energy efficient self-adaptive Bloom filter for network packet processing

Future Internet requires re-thinking of network infrastructure towards the balance between computing capacities and energy sustainable techniques. As one of computing intensive components, Bloom filters are widely used for network packet processing. In this paper, an energy efficient self-adaptive Bloom filter, EABF, is devoted to a balance of power and performance especially for high performance networks. The basic idea is to give the Bloom Filter the capability to adjust the number of active hash functions according to the current workload automatically. This adaption depends on its control policies. Three policies are presented and compared. We also give the method to implement EABF in hardware for higher performance. It is presented in a two-stage platform based on FPGA where Stage 1 is always active and Stage 2, a secondary stage, is only active when necessary. The platform can also be extended to multi-stages. A control circuit is designed for flexibly changing working stage and reducing both dynamic and static power consumption. Analysis and experiments show that our dynamic two-stage EABF can achieve almost the best power savings as that of the fixed schemes; unlike the fixed schemes that might have much longer latency, EABF maintains nearly 1 clock cycle latency as that of a regular Bloom filter.

Enhancing Scalable Name-Based Forwarding

Name-based forwarding is a core component in information-centric networks. Designing scalable name-based forwarding solutions is challenging because name prefixes are of variable length and the forwarding tables can be much longer than seen with IP. Recently, the speculative forwarding method has been proposed, in which the forwarding structure size is proportional to the information-theoretic differences between the name prefixes rather than their lengths. In this paper, our goal is to enhance name-based forwarding performance with memory-and time-efficient data structures. We first define the string differentiation problem, based on the behavior of speculative forwarding in core networks, and then propose fingerprint-based solutions for both trie-based and hash table-based data structures. We experimentally demonstrate that the proposed solutions reduce the lookup latency and memory requirements. The proposed fingerprint-based Patricia trie decreases the average leaf-node depth and thus reduces the lookup latency. The proposed fingerprint-based hash table design requires only 3.2 GB of memory to store 1 billion names where each name has only one name component, and the measured lookup latency of the software-based single-threaded implementation is 0.29 microseconds. Whats more, the distributed forwarding scheme presented in this paper makes name-based forwarding truly scalable.

File-Aware P2P Traffic Classification and Management

As P2P dominates Internet traffic in recent years, ISPs are striving to balance between providing the basic networking service for P2P users and properly managing network bandwidth usage. However, current P2P traffic management strategies are unable to satisfy both requirements. A file-aware P2P traffic classification method is presented in this paper. It can identify a file and the associated flows. Based on the file-level concurrent flow information, ISPs can adopt more efficient and flexible strategies to manage P2P traffic. We offered two alternatives: limiting the aggregated bandwidth consumption or the number of concurrent flows that a peer can use to download a particular file.

A path combinational method for multiple pattern matching

Multiple pattern matching architecture is critical for content inspection based network security applications, especially for high speed network or large pattern sets. This paper presents a method to optimize the potential memory usage for multiple string or regular expression matching by the idea of combining DFAs paths, named isomorphic path combination (IMPC). To achieve IMPC, a novel multiple pattern matching algorithm is proposed, which is based on Cached DFA (CDFA). Compared to extended AC algorithm based on DFA, our method on CDFA can reduce 78.6% states for Snort pattern set, which results in one of the most memory efficient methods. More important is that our method can be embedded to other algorithms as the optimization.