Tiberiu Seceleanu

Segment arbiter as action system

The latest improvements in the technology of digital devices allow designers to build whole systems on a single silicon chip. New problem arise in this context, one of them being the complexity of interconnection. Problematic issues are global clock signal distribution and design composability, for which asynchronous design methodology proves to be a good solution. This study analyzes bus-modeling aspects in the formal framework of action systems.

Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers

Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router buffers. Resource sharing for on-chip network is critical to reduce the chip area and power consumption. Virtual channel buffer sharing by other router ports has been proposed to enhance the performance of on-chip communication. We approach the router architecture optimization by utilizing the idle buffers instead of increasing the number and size of buffers for desired throughput.

The SegBus platform - architecture and communication mechanisms

In this study, we introduce the SegBus architecture, a synchronous segmented bus platform for systems on chip. We present the envisioned structure in detail, and also address aspects of communication on the platform. The motivation behind SegBus is the search for performance improvements, in several directions, such as global throughput, power consumption, modularity, adaptability. By means of an example, we illustrate the capabilities of the described architecture. The implementation strategy targets FPGA technology, and allows for the utilization of multiple clock domains. The platform emerges as a highly design-time configurable system, adaptable to various design constraints.

Resource allocation methodology for the segmented bus platform

Consider a system-on-chip platform realized around the concept of segmented bus structure. The bus is segmented in such a way that modules connected to a particular segment of the bus can communicate in parallel with the data transfer operations going on in the other segments. Given the frequency of data transfer operations between the modules, our task is to determine an efficient segmentation and segment-to-module assignment of this kind of system organization. We consider several different optimization methods for the problem and demonstrate their use for sample cases, both theoretically and practically.

PVS-NoC: Partial Virtual Channel Sharing NoC Architecture

A novel architecture aiming for ideal performance and overhead tradeoff, PVS-NoC (Partial VC Sharing NoC), is presented. Virtual channel (VC) is an efficient technique to improve network performance, while suffering from large silicon and power overhead. We propose sharing the VC buffers among dual inputs, which provides the performance advantage as conventional VC-based router with minimized overhead. We reason theoretically and demonstrate quantitatively the benefits of proposed architecture by comparing to state-of-the-art NoC routers, with various traffic patterns. Extensive experiments with synthetic and real benchmarks show significant area and power saving with similar performance compared to latest VC based NoC architectures.

A Model-Based Design Process for the SegBus Distributed Architecture

We discuss a design process for a custom distributed platform, namely the SegBus segmented bus architecture. The main emphasis of this work is on how different steps of the process are interconnected and how they are supported by the associated tool chain. We place the SegBus design process in the context of the model-driven architecture (MDA) paradigm, in order to provide graphical editors that allow the editing of the specification at different abstraction levels and automated transformations that refine the specification towards implementation. We customize the Unified Modeling Language (UML) to graphically specify different artifacts produced in the process and we employ UML-based tools to implement transformations between these artifacts. In addition, we adopt as application model the packet SDF (PSDF), an extension of the synchronous data flow (SDF) diagrams. By modeling the operational semantics for the SegBus architecture, the PSDF facilitates the mapping of the application on the architecture. From the mapping process we obtain the requirements for the structural VHDL code of the application-platform instance realization and the control code for the arbiters of the architecture.

Implementation of a self-timed segmented bus

We propose an asynchronous structure for implementation on a SoC. An intersegment topological arrangement preserves parallelization and, through a so-called central arbiter, efficiently organizes communication with high signaling speed in the proposed structure. Researchers proposed the concept of segmenting buses primarily for multicomputer architectures. More recent approaches address on-chip implementation of segmented buses. We present an asynchronous segmented-bus architecture targeted for the modular design of high-performance SoC applications. The structure not only enables faster operation than a conventional bus system but also offers lower power consumption per transferred data item. This is possible because segmentation is realized in such a way that the majority of data transfers in the system are intrasegment transactions on relatively short wires with low or moderate capacitive loads.

Towards a Model-Based Approach for Allocating Tasks to Multicore Processors

Multicore technology provides a way to improve the performance of embedded systems in response to the demand in many domains for more and more complex functionality. However, increasing the number of processing units also introduces the problem of deciding which task to execute on which core in order to best utilize the platform. In this paper we present a model-based approach for automatic allocation of software tasks to the cores of a soft real-time embedded system, based on design-time performance predictions. We describe a general iterative method for finding an allocation that maximizes key performance aspects while satisfying given allocation constraints, and present an instance of this method, focusing on the particular performance aspects of timeliness and balanced computational load over time and over the cores.

Communication on a segmented bus

In this study, we discuss communication aspects concerning a segmented bus platform. Placed somewhere midway between the classical system bus and the network on chip approaches, the segmented bus architecture provides certain performance improvements in comparison with the first, while employing a much simpler communication structure and algorithm than those thought for the second. Our implementation strategy targets an FPGA technology. The result comes as a parameterized communication scheme for system on chip designers.

Application development flow for on-chip distributed architectures

We approach the construction of design methodologies for on-chip multiprocessor platforms, with the focus on the SegBus, a segmented bus platform. We study how applications can be mapped on such distributed architecture and show how to build the concrete level software procedures that will coordinate the control flow on the platform. The approach employs models developed in the Matlab-Simulink environment considering also a unified representation of both platform and application. The running example is represented by the H.264 encoder. Allocation of processing elements on the platform, structure and functionality and the eventual control code for arbiters are the main topics described here.