Tien-Hao Tang

High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

The dependence of device structures and layout parameters on ESD robustness of HV MOSFETs in high-voltage 40-V CMOS process has been investigated by device simulation and verified in silicon test chips. It was demonstrated that a new ESD protection structure with p-type SCR embedded into the HV PMOS has the highest ESD robustness in a given 40-V CMOS process.

Latch-up free ESD protection design with SCR structure in advanced CMOS technology

An electrostatic discharge (ESD) protection circuit with silicon-controlled-rectifier (SCR) device has been designed without latch-up risk. After fabrication in a 0.13-µm CMOS process, the ESD protection circuit with SCR width of 60µm can sustain 6.2kV human-body-model (HBM) and 475V machine model (MM) ESD tests. The latch-up test shows the immunity against 500-mA triggering current under 3.3V supply voltage.

ESD protection design with lateral DMOS transistor in 40-V BCD technology

ESD protection designs for smart power applications with lateral double-diffused MOS (LDMOS) transistor were proposed. With the proposed ESD detection circuits, the n-channel LDMOS can be quickly turned on to protect the output drivers during ESD stress. The proposed ESD protection circuits have been successfully verified in a 0.35-µm 5-V/40-V bipolar CMOS DMOS (BCD) process. In addition, the power-rail ESD protection design can be also achieved with stacked structure to protect 40-V power pins without latchup issue in the smart power ICs.

ESD Robustness of 40-V CMOS Devices With/Without Drift Implant

The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased

Optimization of PESD implant design for ESD robustness of 5V drain-back N-LDMOSFET

An N-LDMOS ESD protection device with drain back and PESD optimization design is proposed. With PESD layer enclosing the N+ drain region, a parasitic SCR is created to achieve high ESD level. When PESD is close to gate, the turn-on efficiency can be further improved (Vt1: 11.2 V reduced to 7.2 V) by the punch-through path from N+/PESD to PW. The proposed ESD N-LDMOS can sustain over 8KV HBM with low trigger behavior without extra area cost.

Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes

A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1timesVDD devices for 3timesVDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-mum CMOS process with only 1.2-V devices.

A novel high level ESD FDNSCR with drain side engineering in PMIC application

In order to develop cost-effective System-on-Chip (SoC) solutions, it is important to implement High-Voltage (HV) tolerant devices using standard CMOS technologies for varied applications, such as display and LED drivers, flash memories, automotive applications etc. However, the on-chip ESD protection designs are required to provide higher robustness to prevent chip from ESD damage. Silicon Controlled Rectifiers (SCR) have been widely used, because of their superior area-efficient ESD robustness [1-3]. However, lower failure current It2 has been observed during ESD stress on Field Drift MOSFET Silicon Controlled Rectifier (FDNSCR) devices in 0.18μm BCD epi process. The root cause of early failure is related to low turn-on efficiency of SCR during ESD stress.

Design of modified ESD protection structure with low-trigger and high-holding voltage in embedded high voltage CMOS process

The modified ESD protection structure with N-well implant in the drain region has been proposed and investigated in this paper. Table I lists the comparison of TLP, HBM/MM ESD robustness, and TLU immunity between HV GGNMOS structure with and without N-well implant. By the influence of N-well implant, many drawbacks such as double snapback, soft leakage degradation, non-uniform current conduction, low ESD robustness, and weak TLU immunity in the common HV GGNMOS device are overcome efficaciously. Without additional mask or process cost, the proposed ESD device with low trigger voltage and high holding voltage is effectively employed for power clamp protection in HV CMOS ICs without latchup or transient-induced latchup damage.

Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (VBD) and low holding voltage (Vh) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM>8kV) and good turn-on efficiency (Vt1=8.1V) without suffering from low VBD and latch-up issues.

Lower trigger voltage design for ESD protection device applied in PMIC application

Lower trigger voltage ESD protection has been designed in PMIC application process. The proposed design lowers trigger voltage around 11% without extra mask layer and the layout diagram is simple and clear. The proposed device can be turned on quickly to protect the large array in output buffer design safely. It sustains 3.8kV human-body-model (HBM) and 350V machine model (MM) ESD tests, respectively.