Timo D. Hämäläinen

A survey of application distribution in wireless sensor networks

Wireless sensor networks (WSNs) are deployed to an area of interest to sense phenomena, process sensed data, and take actions accordingly. Due to the limited WSN node resources, distributed processing is required for completing application tasks. Proposals implementing distribution services for WSNs are evolving on different levels of generality. In this paper, these solutions are reviewed in order to determine the current status. According to the review, existing distribution technologies for computer networks are not applicable for WSNs. Operating systems (OSs) and middleware architectures for WSNs implement separate services for distribution within the existing constraints but an approach providing a complete distributed environment for applications is absent. In order to implement an efficient and adaptive environment, a middleware should be tightly integrated in the underlying OS. We recommend a framework in which a middleware distributes the application processing to a WSN so that the application lifetime is maximized. OS implements services for application tasks and information gathering as well as control interfaces for the middleware.

Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core

The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption hardware core suited for devices in which low cost and low power consumption are desired. The core constitutes of a novel 8-bit architecture and supports encryption with 128-bit keys. In a 0.13 mum CMOS technology our area optimized implementation consumes 3.1 kgates. The throughput at the maximum clock frequency of 153 MHz is 121 Mbps, also in feedback encryption modes. Compared to previous 8-bit implementations, we achieve significantly higher throughput with corresponding area. The energy consumption per processed block is also lower

Genetic Algorithm to Optimize Node Placement and Configuration for WLAN Planning

This paper presents a novel algorithm to rapidly create a high quality network plan for IEEE 802.11 based WLAN according to assigned design requirements. The algorithm uses a Genetic Algorithm (GA) to explore the design space, and a IEEE 802.11 rate adaptation aware QoS estimation functionality to provide feedback for the algorithm and for a network designer. The algorithm selects AP devices, locations, antennas, as well as AP configuration including transmission power and frequency channel. The algorithm was used in WLAN planning for a suburb, which is under development in Tampere-Lempaala area in Finland. Compared to manual network planning, the developed algorithm was able to create a network plan with 133 % capacity, 98 % coverage, and 93 % cost. Manually the corresponding network planning took hours, whereas the algorithm computation time was 15 minutes.

Comparative Rate-Distortion-Complexity Analysis of HEVC and AVC Video Codecs

This paper analyzes the rate-distortion-complexity of High Efficiency Video Coding (HEVC) reference video codec (HM) and compares the results with AVC reference codec (JM). The examined software codecs are HM 6.0 using Main Profile (MP) and JM 18.0 using High Profile (HiP). These codes are benchmarked under the all-intra (AI), random access (RA), low-delay B (LB), and low-delay P (LP) coding configurations. In order to obtain a fair comparison, JM HiP anchor codec has been configured to conform to HM MP settings and coding configurations. The rate-distortion comparisons rely on objective quality assessments, i.e., bit rate differences for equal PSNR. The complexities of HM and JM have been profiled at the cycle level with Intel VTune on Intel Core 2 Duo processor. The coding efficiency of HEVC is drastically better than that of AVC. According to our experiments, the average bit rate decrements of HM MP over JM HiP are 23%, 35%, 40%, and 35% under the AI, RA, LB, and LP configurations, respectively. However, HM achieves its coding gain with a realistic overhead in complexity. Our profiling results show that the average software complexity ratios of HM MP and JM HiP encoders are 3.2× in the AI case, 1.2× in the RA case, 1.5× in the LB case, and 1.3× in the LP case. The respective ratios with HM MP and JM HiP decoders are 2.0×, 1.6×, 1.5×, and 1.4×. This paper also reveals the bottlenecks of HM codec and provides implementation guidelines for future real-time HEVC codecs.

Performance analysis of IEEE 802.15.4 and ZigBee for large-scale wireless sensor network applications

This paper analyses the performance of IEEE 802.15.4 Low-Rate Wireless Personal Area Network (LR-WPAN) in a large-scale Wireless Sensor Network (WSN) application. To minimize the energy consumption of the entire network and to allow adequate network coverage, IEEE 802.15.4 peer-to-peer topology is selected, and configured to a beacon-enabled cluster-tree structure. The analysis consists of models for CSMA-CA mechanism and MAC operations specified by IEEE 802.15.4. Network layer operations in a cluster-tree network specified by ZigBee are included in the analysis. For realistic results, power consumption measurements on an IEEE 802.15.4 evaluation board are also included. The performances of a device and a coordinator are analyzed in terms of power consumption and goodput. The results are verified with simulations using WIreless SEnsor NEtwork Simulator (WISENES). The results depict that the minimum device power consumption is as low as 73 μW, when beacon interval is 3.93 s, and data are transmitted at 4 min intervals. Coordinator power consumption and goodput with 15.36 ms CAP duration and 3.93 s beacon interval are around 370 μW and 34 bits/s

UML-based multiprocessor SoC design framework

This paper describes a complete design flow for multiprocessor systems-on-chips (SoCs) covering the design phases from system-level modeling to FPGA prototyping. The design of complex heterogeneous systems is enabled by raising the abstraction level and providing several system-level design automation tools. The system is modeled in a UML design environment following a new UML profile that specifies the practices for orthogonal application and architecture modeling. The design flow tools are governed in a single framework that combines the subtools into a seamless flow and visualizes the design process. Novel features also include an automated architecture exploration based on the system models in UML, as well as the automatic back and forward annotation of information in the design flow. The architecture exploration is based on the global optimization of systems that are composed of subsystems, which are then locally optimized for their particular purposes. As a result, the design flow produces an optimized component allocation, task mapping, and scheduling for the described application. In addition, it implements the entire system for FPGA prototyping board. As a case study, the design flow is utilized in the integration of state-of-the-art technology approaches, including a wireless terminal architecture, a network-on-chip, and multiprocessing utilizing RTOS in a SoC. In this study, a central part of a WLAN terminal is modeled, verified, optimized, and prototyped with the presented framework.

Experiments on local positioning with Bluetooth

This paper presents the design and implementation of the Bluetooth local positioning application. Positioning is based on received power levels, which are converted to distance estimates according to a simple propagation model. The extended Kalman filter computes a 3D position estimate on the basis of distance estimates. With the used Bluetooth hardware, the mean absolute error of positioning was measured to be 3.76 m. The accuracy can be improved if Bluetooth devices are able to measure received power levels more precisely.

Complexity of optimized H.26L video decoder implementation

An analysis of computational complexity is presented for an H.26L video decoder, based on extensive experiments on a general-purpose processor. In addition, platform-independent techniques to optimize an H.26L decoder implementation are given. Comparisons are carried out between our highly optimized version of H.26L, the public reference implementation of H.26L, and a highly optimized H.263+ implementation. Both QCIF and CIF-sized image sequences are used. The results show that with equal visual quality, the bit-rate savings range from 28% to 58%, while the frame decoding speed of H.26L is about 11% better than that of a highly optimized H.263+.

A High-Performance Sum of Absolute Difference Implementation for Motion Estimation

This paper presents a high-performance sum of absolute difference (SAD) architecture for motion estimation, which is the most time-consuming and compute-intensive part of video coding. The proposed architecture contains novel and efficient optimizations to overcome bottlenecks discovered in existing approaches. In addition, designed sophisticated control logic with multiple early termination mechanisms further enhance execution speed and make the architecture suitable for general-purpose usage. Hence, the proposed architecture is not restricted to a single block-matching algorithm in motion estimation, but a wide range of algorithms is supported. The proposed SAD architecture outperforms contemporary architectures in terms of execution speed and area efficiency. The proposed architecture with three pipeline stages, synthesized to a 0.18-mum CMOS technology, can attain 770-MHz operating frequency at a cost of less than 5600 gates. Correspondingly, performance metrics for the proposed low-latency 2-stage architecture are 730 MHz and 7500 gates

Efficient Mode Decision Schemes for HEVC Inter Prediction

The emerging High Efficiency Video Coding (HEVC) standard reduces the bit rate by almost 40% over the preceding state-of-the-art Advanced Video Coding (AVC) standard with the same objective quality but at about 40% encoding complexity overhead. The main reason for HEVC complexity is inter prediction that accounts for 60%-70% of the whole encoding time. This paper analyzes the rate-distortion-complexity characteristics of the HEVC inter prediction as a function of different block partition structures and puts the analysis results into practice by developing optimized mode decision schemes for the HEVC encoder. The HEVC inter prediction involves three different partition modes: square motion partition, symmetric motion partition (SMP), and asymmetric motion partition (AMP) out of which the decision of SMPs and AMPs are optimized in this paper. The key optimization techniques behind the proposed schemes are: 1) a conditional evaluation of the SMP modes; 2) range limitations primarily in the SMP sizes and secondarily in the AMP sizes; and 3) a selection of the SMP and AMP ranges as a function of the quantization parameter. These three techniques can be seamlessly incorporated in the existing control structures of the HEVC reference encoder without limiting its potential parallelization, hardware acceleration, or speed-up with other existing encoder optimizations. Our experiments show that the proposed schemes are able to cut the average complexity of the HEVC reference encoder by 31%-51% at a cost of 0.2%-1.3% bit rate increase under the random access coding configuration. The respective values under the low-delay B coding configuration are 32%-50% and 0.3%-1.3%.