Timo Sandmann

Hardware virtualization support for shared resources in mixed-criticality multicore systems

Electric/Electronic architectures in modern automobiles evolve towards an hierarchical approach where functionalities from several ECUs are consolidated into few domain computers. Performance requirements directly lead to multicore solutions but also to a combination of very different requirements on such ECUs. Using virtualization in addition is one promising way of achieving segregation in time and space of shared resources. Based on examples taken from the automotive domain several concepts for efficient hardware extensions of coprocessors and I/O devices are shown in this contribution. These provide mechanisms to ensure quality of service (QoS) levels in terms of execution time, throughput and latency. The resulting infotainment architecture is a feasibility study and is integrated into a vehicle demonstrator as centralized infotainment platform (VCT).

Virtualization Support for FPGA-Based Coprocessors Connected via PCI Express to an Intel Multicore Platform

In automotive electronics, the approach to integrate several existing single-core electronics control units into a multicore computer platform is now emerging. The integration may result in mixed-criticality systems where robust segregation between software applications is crucial. Another requirement for this process is the reusability of legacy software. Virtualization is a promising technique which can help to solve these problems. In this paper, we present a hardware software co-designed virtualization support for FPGA-based coprocessors, which are connected via PCI Express to an Intel multicore platform. Experimental results show that our approach outperforms completely software-based virtualization approaches by upto 3.13 times for read and upto 26.26 times for write operations.

A flexible interface architecture for reconfigurable coprocessors in embedded multicore systems using PCIe Single-root I/O virtualization

Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In this paper, we propose a flexible interface architecture with low overhead for coupling reconfigurable coprocessors to high-performance general-purpose processors, allowing customized yet efficient construction of heterogeneous processing systems. Our implementation is based on PCI Express (PCIe) and optimized for virtualized systems, taking advantage of the SR-IOV capabilities in modern PCIe implementations. We describe the interface architecture and its fundamental technologies, detail the services provided to individual coprocessors and accelerator modules, and quantify key corner performance indicators relevant for virtualized applications.

Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualization

Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In this paper, we propose a concept that leverages the advantages of FPGAs partial reconfiguration in heterogeneous mixed criticality multicore systems. We describe the basic idea how to handle the partial reconfiguration transparently for non-critical tasks, while providing full control and a predictable behavior for safety relevant tasks. Our prototype is implemented on an Intel multicore system and a Xilinx Virtex-7 FPGA connected via PCI Express (PCIe), taking advantage of the Single-Root I/O Virtualization (SR-IOV) capabilities in modern PCIe implementations. Preliminary experimental results show that our concept achieves significantly shorter reconfiguration time with lower variance compared to other solutions.

Adapting Commercial Off-The-Shelf Multicore Processors for Safety-Related Automotive Systems Using Online Monitoring

Multicores, being the latest state-of-the-art technology, gain more and more importance in automotive and aerospace systems. This technology will not only be used in infotainment and non-safety-critical applications but will also be introduced in upcoming safety-critical systems. At the moment, various commercial off-the-shelf processors are available that are, however, not built for such applications. In order to ensure correct system behavior, online monitoring can be used for processors targeting infotainment or general purpose applications. The cores and other bus masters within the MPSoC compete for the exclusive use of shared resources like a memory controller. It is of high importance to provide guarantees of usage in such cases, e.g. in terms of access time and rates. For this purpose we present an online monitoring based on a commercial off-the-shelf multicore processor that provides knowledge about the usage of the direct memory access (DMA) controller in terms of accesses and activation sources. Furthermore, with this information, conclusions about the memory controller workload are drawn. The concept is implemented by using Freescale’s i.MX6 Quad platform, which is targeting automotive infotainment. This paper aims to show how such general purpose multicore processors can be partly adapted to provide evidence for safety related systems.

Programmable Logic as Device Virtualization Layer in Heterogeneous Multicore Architectures

In latest heterogeneous multicore architectures, the number of cores competing for a shared resource is further increasing. Such shared resources range from simple I/O interfaces to memory controllers. The performance of the complete System-On-Chip SoC is directly correlated to the sharing of resources. Especially the hardly predictable blocking of resources for a certain time, forces the system to slow down in a way that is not intended. Hence new concepts for the sharing of resources need to be developed. The use of virtualization provides possibilities to handle the sharing of resources but always introduces an overhead in software in form of a hypervisor and also needs support on hardware level. In this contribution we explore the idea of using the FPGA fabric as intermediate hardware virtualization layer between the cores and existing peripherals in a heterogeneous multicore SoC. This paper applies the idea exemplarily to Controller Area Network CAN virtualization, including concept and evaluation. We show the transparency of a virtualization layer and its introduction with low overhead of area and latency, which might serve as efficient add-on in a virtualized environment.

On-demand reconfiguration for coprocessors in mixed criticality multicore systems

Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In a previous work, we proposed a concept that leverages the advantages of FPGAs partial reconfiguration in heterogeneous mixed criticality multicore systems. The basic idea how to handle the partial reconfiguration transparently for noncritical tasks, while providing full control and a predictable behavior for safety relevant tasks was described. In this paper, we focus on the on-demand partial reconfiguration of coprocessors and its implementation details. Our prototype is implemented on an Intel multicore system and a Xilinx Virtex-7 FPGA connected via PCI Express, taking advantage of the Single-Root I/O Virtualization capabilities in modern PCI Express implementations. Experimental results show that compared to the reference software implementation, our concept achieves significantly shorter reconfiguration time with lower variance under various system load situations.

Architectural measures against radiation effects in multicore SoC for safety critical applications

It is well known that microelectronics sensitivity for radiation effects steadily increases for smaller structure sizes. Additionally lowering the supply voltage decreases safety margins even further. In conclusion modern System-on-Chip (SoC) devices, which typically come as heterogeneous multicores, can be affected by radiation effects not only in space but also in much lower altitudes or even on ground level. This is especially important for safety critical systems, such as automotive or avionics electronics. In order to cope with this issue measures during all phases of development need to be taken into account. This contribution presents and discusses techniques on architectural level, which help to detect faults on the SoC, which might be caused by (but not solely) radiation effects. Additionally these techniques have to be lightweight in terms of resources and costs as safety critical applications typically target cost sensitive markets.

Hardware/software trade-offs for shared resources virtualization in mixed-criticality automotive multicore systems

Abstract Virtualization plays an important role for embedded systems where hardware support can prove beneficial, but these systems also pose a challenge due to power, resource constraints; reliability, safety, real-time requirements; diversity of devices, and operating systems. Therefore a trade-off between flexibility, determinism and performance exists in the embedded application domain. As virtualization in software always incurs overhead due to context switching, interrupt handling, etc. the aim is to minimize the overhead and make execution more deterministic using hardware support.

Two Architecture Approaches for MILS Systems in Mobility Domains (Automobile, Railway and Avionik)

Systems with mixed and independent levels of security and safety become more and more important in the future. In the German funded Bundesministerium fur Bildung und Forschung (BMBF) research project ARAMiS (Automotive, Railway and Avionic Multicore Systems) different industry and scientific partners concerned on using multi-core processor for different security and safety critical use-cases. This paper describes the motivation and use-cases behind the research actives in different mobility domains. Also two detailed descriptions and a comparison of two implementation for Multiple Independent Levels of Security and Safety (MILS) systems in mobility domains are included. In the end of the paper a outlook is given on potential further research activities on this research topic.