Timothy C. Bronson

System and method for interrupt command queuing and ordering

System and method for supporting access to multiple I/O hub nodes in a host bridge

Data caching on bridge following disconnect

System and method for sharing I/O address translation caching across multiple host bridges

System and method for loading commands to a bus, directly loading selective commands while queuing and strictly ordering other commands

System and method for implementing private devices on a secondary peripheral component interface

Phase locked loop reconfiguration

System and method for detecting phase errors in asics with multiple clock frequencies

Cache bank modeling with variable access and busy times

Opaque memory region for I/O adapter transparent bridge