Timothy O. Dickson

30-100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits

Silicon planar and three-dimensional inductors and transformers were designed and characterized on-wafer up to 100 GHz. Self-resonance frequencies (SRFs) beyond 100 GHz were obtained, demonstrating for the first time that spiral structures are suitable for applications such as 60-GHz wireless local area network and 77-GHz automotive RADAR. Minimizing area over substrate is critical to achieving high SRF. A stacked transformer is reported with S/sub 21/ of -2.5 dB at 50 GHz, and which offers improved performance and less area (30 /spl mu/m/spl times/30 /spl mu/m) than planar transformers or microstrip couplers. A compact inductor model is described, along with a methodology for extracting model parameters from simulated or measured y-parameters. Millimeter-wave SiGe BiCMOS mixer and voltage-controlled-oscillator circuits employing spiral inductors are presented with better or comparable performance to previously reported transmission-line-based circuits.

The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks

This paper provides evidence that, as a result of constant-field scaling, the peak fT (approx. 0.3 mA/mum), peak fMAX (approx. 0.2 mA/mum), and optimum noise figure NFMIN (approx. 0.15 mA/mum) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers

An 80-Gb/s 2/sup 31/-1 pseudorandom binary sequence generator in SiGe BiCMOS technology

A 2/sup 31/-1 pseudorandom binary sequence (PRBS) generator with adjustable output data rates up to 80 Gb/s is reported in a production 130-nm BiCMOS process with 150-GHz f/sub T/ SiGe heterojunction bipolar transistor (HBT). The pseudorandom sequence is generated at 20 Gb/s using a linear feedback shift register (FSR), which is then multiplexed up to 80 Gb/s with a 4:1 multiplexer. A BiCMOS logic family combining MOSFETs and SiGe HBTs on high-speed paths is employed throughout the PRBS generator to maximize building block switching speed. Adjustable delay cells are inserted into critical clock paths to improve timing margins throughout the system. The PRBS generator consumes 9.8 W from a 3.3-V supply and can deliver an output voltage swing of up to 430 mV single-ended at 80 Gb/s.

A comparison of Si CMOS, SiGe BiCMOS, and InP HBT technologies for high-speed and millimeter-wave ICs

The paper presents an overview of Si MOSFET, SiGe HBT, and InP HBT device and circuit performance for broadband and tuned millimeter-wave applications. Implementations of CMOS-only, SiGe-HBT-only, SiGe BiCMOS, and InP-HBT 30-80 Gb/s high-speed circuit in production 130-nm SiGe BiCMOS and InP HBT technologies are compared.

High-Speed SiGe BiCMOS Technologies: 120-nm Status and End-of-Roadmap Challenges

This paper presents the status of high-speed SiGe BiCMOS technologies at STMicroelectronics. Process and electrical characteristics of two 120-nm platforms, qualified or under development, are presented together with results demonstrated on optical and millimeter-wave circuits. Advanced developments addressing end-of-roadmap BiCMOS are also presented and discussed

A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic

A 45-Gb/s BiCMOS decision circuit operating from a 2.5-V supply is reported. The full-rate retiming flip-flop operates from the lowest supply voltage of any silicon-based flip-flop demonstrated to date at this speed. MOS and SiGe heterojunction-bipolar-transistor (HBT) current-mode logic families are compared. Capitalizing on the best features of both families, a true BiCMOS logic topology is presented that allows for operation from lower supply voltages than pure HBT implementations without compromising speed. The topology, based on a BiCMOS cascode, can also be applied to a number of millimeter-wave (mm-wave) circuits. In addition to the retiming flip-flop, the decision circuit includes a broadband transimpedance preamplifier to improve sensitivity, a tuned 45-GHz clock buffer, and a 50-/spl Omega/ output driver. The first mm-wave transformer is employed along the clock path to perform single-ended-to-differential conversion. The entire circuit, which is implemented in a production 130-nm BiCMOS process with 150-GHz f/sub T/ SiGe HBT, consumes 288 mW from a 2.5-V supply, including only 58 mW from the flip-flop.

A 1.5V 20/30 Gb/s CMOS backplane driver with digital pre-emphasis

A high-speed input comparator and output driver with adjustable pre-emphasis for applications in serial interchip communications over backplanes at 20 Gb/s is presented. The circuit was implemented in 130-nm CMOS and consumes 140 mW from a 1.5-V supply. It has over 30 dB dynamic range with a sensitivity of 20 mVp-p and a differential output swing of 700 mVp-p at 20 Gb/s. The output driver features a novel digital pre-emphasis circuit with independent pulse height and width control. Other features include 30%-70% eye-crossing control and adjustable output swing between 170 mVp-p and 350 mVp-p per side at data rates up to 30 Gb/s.

Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes

This paper presents an analysis of sub-2.5-V topologies and design methodologies for SiGe BiCMOS and sub-90nm CMOS building blocks to be used in the next generation of 40-100 Gb/s wireline transceivers. Examples of optimal designs for 40-80Gb/s broadband low-noise input comparators, low-voltage high-speed MOS- and BiCMOS CML logic gates, 30-100 GHz low-noise oscillators, and 40/80 GHz output drivers with wave shape control are provided.

A 2.5-V, 40-Gb/s decision circuit using SiGe BiCMOS logic

A 40-Gb/s decision circuit is reported which operates from a 2.5-V supply. It includes a flip-flop, a broadband transimpeclance preamplifier, a tuned 40-GHz clock buffer, and a 50-/spl Omega/ output driver. The flipflop features a novel BiCMOS CML logic topology, which allows for lower supply voltages as compared with pure bipolar implementations without compromising speed. A mm-wave transformer is used to perform single-ended-to-differential conversion along the 40 GHz clock path.

Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS

Low-power building blocks for a serial transmitter operating up to 86 Gb/s are designed and implemented in a 130-nm SiGe BiCMOS technology with 150-GHz fT SiGe HBT. Power reduction is achieved by employing a low-voltage 2.5-V BiCMOS logic family, and by trading off bias current for inductive peaking. A serial transmitter test chip is fabricated in a 130-nm, 150-GHz fT SiGe BiCMOS technology. Operation is verified up to 86 Gb/s at room temperature (92Gb/s and 71Gb/s at 0degC and 100degC, respectively). As compared to recent state-of-the-art CMOS results, this work shows that by adding a SiGe HBT to a CMOS process one can achieve double the data rate with half the power dissipation