Ting-Ting Y. Lin

A general purpose multiple way partitioning algorithm

This pper presents a discussion of methods to solve multiple way partitioning problems under three different objective functions. A multicommodity flow treatment is proposed for partitioning without a size constraint, and an iterative improvement algorithm is proposed for partitioning with a size constlaint. This algorithm incorporates a top-down clustering technique to deal with the local minima problems in common heuristics, a novel multi-pin net model to capture the contributory moves, and a Primal-hal iteration to enhance the iterative improvement. Experiments show good results in all tested cases over the algorithm proposed in [12]. Also, the effect of different objective functions is manifested through numerical tabulation.

A probabilistic multicommodity-flow solution to circuit clustering problems

Circuit clustering, which plays a fundamental role in hierarchical designs, is discussed. Identifying strongly connected components in the circuits can significantly reduce the complexity of the design and improve the performance of the design process. However, there has not been a clear objective function for circuit clustering. A clustering metric based on the random graph model and the ratio cust concept is presented. A probabilistic, multicommodity flow based algorithm is proposed and tested under the clustering metric. Experimental results show that this algorithm generates promising results with respect to the proposed metric. Extensions and directions for future work are also proposed.<<ETX>>

Optimization by iterative improvement: an experimental evaluation on two-way partitioning

Recently, Johnson et al. [1989] presented an excellent comparison of simulated annealing and Kernighan-Lin algorithms. However, their test beds were limited to random and geometric graphs. We present a complete evaluation by adding real circuitry into the test beds. A two-level partitioning algorithm called the primal-dual algorithm is also incorporated for comparison. We show that at least 500 runs are necessary to demonstrate the performance of the Fiduccia-Mattheyses algorithm, whereas traditional way of evaluation tends to underestimate. Nevertheless, our new results show that for two-way partitioning on real circuits, the primal-dual algorithm is, in general, a better choice than both the Fiduccia-Mattheyses algorithm and the simulated annealing algorithm. This conclusion is more likely to hold when the primal-dual algorithm is switched to a simpler mode. >

A general purpose, multiple-way partitioning algorithm

Multiple-way partitioning is an important extension of two-way partitioning as it provides a more natural and direct model for many partitioning applications. In this paper, we discuss several objective functions derived from such an extension and propose an iterative improvement algorithm to solve the multiple-way partitioning problem. The algorithm proceeds in three phases. The first phase employs a recursive ratio-cut scheme to group highly connected subcircuits into clusters. The second phase performs iterative improvement on the clustered circuit using a Dew net-based move model and a Primal-Dual refinement procedure. The third phase is the same as the second phase except that the iterative improvement is done on the original circuit. Experiments show good results in all tested cases. >

Circuit clustering using a stochastic flow injection method

We present a new clustering metric, based on a random graph model and a ratio cut concept. The minimization of the proposed clustering cost can be transformed to a uniform multicommodity flow problem by adding artificial weight functions, which can be solved by a multicommodity flow-based algorithm with high complexity. We devise a probabilistic flow injection approach which drastically reduces the complexity of the flow-based algorithm. Experimental results show that this algorithm generates promising results with respect to the proposed metric. >

Optimization of power dissipation and skew sensitivity in clock buffer synthesis

Contrary to a common belief that the load capacitance dominates overall power dissipation in the clock net, our experiment found a significant portion (up to 77.4%) of the power dissipation contributed from the interconnect of the clock tree. We introduce a new design concept and an algorithm to optimize both power dissipation and skew sensitivity in the clock buffer synthesis. Using a frequency divider and doublers, we effectively reduce the power dissipated in the clock tree into half. Our efficient algorithm optimizes power dissipation and clock skew sensitivity simultaneously. Our experimental results show an average of 49% reduction of power dissipation while reducing clock skew by several orders of magnitude.

An experimental evaluation of partitioning algorithms

Presents an experimental evaluation of partitioning algorithms to supplement the work done by D.S. Johnson, et al. (1989). MCNC test-cases are used as part of the test beds. A two-level partitioning algorithm is proposed whose performance exceeds that of the algorithm by C.M. Fiduccia, R.M. Mattheyses (1982) on real circuitry by as much as 28%.<<ETX>>

A new framework for designing: built-in test multichip modules with pipelined test strategy

A novel test strategy, the Loop Testing Architecture (LTA), is introduced to reduce aliasing probability and testing time for multichip modules. This is accomplished by connecting cascadable built-in testers (CBITs) in neighboring pipelined stages to increase the length of the test suites. Fundamental properties of the LTA supporting randomness in the generated test patterns (state coverage) and the asymptotic aliasing probability are presented. Results on two small-scale multiprocessor configurations show that the aliasing probability in analyzing signatures is comparable to that of an MLFSR but with fairly low area overhead; compared with the circular self-test path technique, less testing time is required by LTA. Further evaluation of the potential capabilities provided by the LTA compared with boundary scan and other pipelined test scheduling approaches confirmed the usefulness of LTA as a framework for designing effective testable systems.<<ETX>>

Circuit partitioning for pipelined pseudo-exhaustive testing using simulated annealing

A novel approach for partitioning circuits with high fan-ins which are not suitable for pseudo-exhaustive testing is presented. Circuits under test (CUTs) are modeled as directed graphs and cost function is developed for the optimization algorithm. Disjoint circuit partitions are generated not only for reducing the exhaustive test length but also for pipelined testing. Experiments on benchmark circuits demonstrate that simulated annealing produces good results for future applications.<<ETX>>

Evaluation of test strategies for multichip modules

Two parallel testing strategies for multichip modules-the boundary-scan technique and the cascadable built-in tester (CBIT)-are evaluated in terms of testing time, fault coverage, and area overhead. Results on a small-scale processor configuration favor the CBIT design for test effectiveness of the chip, and the boundary-scan design for area overhead interconnection tests.<<ETX>>