Tobias Bjerregaard

A survey of research and practices of Network-on-chip

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

On-chip networks for future system-on-chip designs need simple, high performance implementations. In order to promote system-level integrity, guaranteed services (GS) need to be provided. We propose a network-on-chip (NoC) router architecture to support this, and demonstrate with a CMOS standard cell design. Our implementation is based on clockless circuit techniques, and thus inherently supports a modular GALS-oriented design flow. Our router exploits virtual channels to provide connection-oriented GS, as well as connection-less best-effort (BE) routing. The architecture is highly flexible, in that support for different types of BE routing and GS arbitration can be easily plugged into the router.

Scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip

Guaranteed services (GS) are important in that they provide predictability in the complex dynamics of shared communication structures. This paper discusses the implementation of GS in an asynchronous network-on-chip. We present a novel scheduling discipline called asynchronous latency guarantee (ALG) scheduling, which provides latency and bandwidth guarantees in accessing a shared media, e.g. a physical link shared between a number of virtual channels. ALG overcomes the drawbacks of existing scheduling disciplines, in particular, the coupling between latency and bandwidth guarantees. A 0.12 /spl mu/m CMOS standard cell implementation of an ALG link has been simulated. The operation speed of the design was 702 MDI/s.

Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip

Logically separate channels sharing a physical link, so called virtual channels (VCs), have wide spread uses in multicomputer networks as well as in Network-on-Chip (NoC). This paper presents a number of low overhead VC Implementations, using asynchronous circuit techniques. The designs are highly modular, and can be used to provide access to any shared media. As a demonstration of use, on-chip links providing per connection bandwidth guarantees were implemented.

A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method

Growing system sizes together with increasing performance variability are making globally synchronous operation hard to realize. Mesochronous clocking constitutes a possible solution to the problems faced. The most fundamental of problems faced when communicating between mesochronously clocked regions concerns the possibility of data corruption caused by metastability. This paper presents an integrated communication and mesochronous clocking strategy, which avoids timing related errors while maintaining a globally synchronous system perspective. The architecture is scalable as timing integrity is based purely on local observations. It is demonstrated with a 90 nm CMOS standard cell network-on-chip design which implements completely timing-safe, global communication in a modular system

A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip

We design a very small, packet-switched, clockless network-on-chip (NoC) as a replacement for the existing crossbar-based communication infrastructure in a commercial audio DSP chip. Both solutions are laid out in a 0.18 mum process, and compared in terms of area, power consumption and routing complexity. Even though the NoC turns out to be larger and more power consuming than the existing crossbar implementation, it still accounts for less than 1% of the total chip area and power consumption, and is justified by a long list of advantages: the NoC is modular, scalable and in contrast to the existing crossbar, it allows all blocks to communicate. The total wire length is decreased by 22% which eases the layout process and makes the design less prone to routing congestion. Not least, the communicating blocks are decoupled by means of the NoC, providing a globally-asynchronous, locally-synchronous (GALS) system where independent clocking of the individual blocks is enabled. This study shows that NoCs are feasible even for small systems

A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling

This paper presents the use of SystemC to model communication channels for asynchronous circuits at various levels of abstraction. Our channel library supports transactions through a CSP-like interface (implementing send() and receive() commands) as well as through one of many specific handshake protocols e.g. 4-phase-bundled-data push etc. Our SystemC implementation enables a seamless design flow which makes possible: (i) modeling and simulation at different and mixed levels of abstraction, and (ii) easy use of different data types and handshake protocols on different channels in the circuit being designed. The paper also illustrates the use of this design flow for several asynchronous Networks-on-Chip all the way from system level to handshake components.

A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies

We deliver a design flow for the synthesis and convergence of application-specific networks-on-chip. The flow comes with novel features that can better address nanoscale design challenges: front-end driven floorplanning, dynamic IR-drop minimization, fast and accurate system-level power grid modeling, predictable link design. Above all, such features are addressed by different prototype engines, even from different vendors, that can be smoothly integrated into the flow by means of a common specification format called Communication Exchange Format (CEF), that enables unprecedented tool interactions. This flow is validated by means of an extensive demonstration framework.