Tom Zhong

Perpendicular spin transfer torque magnetic random access memories with high spin torque efficiency and thermal stability for embedded applications (invited)

Magnetic random access memories based on the spin transfer torque phenomenon (STT-MRAMs) have become one of the leading candidates for next generation memory applications. Among the many attractive features of this technology are its potential for high speed and endurance, read signal margin, low power consumption, scalability, and non-volatility. In this paper, we discuss our recent results on perpendicular STT-MRAM stack designs that show STT efficiency higher than 5 kBT/μA, energy barriers higher than 100 kBT at room temperature for sub-40 nm diameter devices, and tunnel magnetoresistance higher than 150%. We use both single device data and results from 8 Mb array to demonstrate data retention sufficient for automotive applications. Moreover, we also demonstrate for the first time thermal stability up to 400 °C exceeding the requirement of Si CMOS back-end processing, thus opening the realm of non-volatile embedded memory to STT-MRAM technology.

A Study of Write Margin of Spin Torque Transfer Magnetic Random Access Memory Technology

Key design parameters of 64 Mb STT-MRAM at 90-nm technology node are discussed. A design point was developed with adequate TMR for fast read operation, enough energy barrier for data retention and against read disturbs, a write voltage satisfying the long term reliability against dielectric breakdown and a write bit error rate below 10-9. A direct experimental method was developed to determine the data retention lifetime that avoids the discrepancy in the energy barrier values obtained with spin current- and field-driven switching measurements. Other parameters detrimental to write margins such as backhopping and the existence of a low breakdown population are discussed. At low bit-error regime, new phenomenon emerges, suggestive of a bifurcation of switching modes. The dependence of the bifurcated switching threshold on write pulse width, operating temperature, junction dimensions and external field were studied. These show bifurcated switching to be strongly influenced by thermal fluctuation related to the spatially inhomogeneous free layer magnetization. An external field along easy axis direction assisting switching was shown to be effective for significantly reducing the percentage of MTJs showing bifurcated switching.

High Spin Torque Efficiency of Magnetic Tunnel Junctions with MgO/CoFeB/MgO Free Layer

We present the results of a perpendicular magnetic tunnel junction (MTJ) that displays simultaneously low critical switching current and voltage, as well as high thermal stability factor. These results were achieved using a free layer of the MgO/CoFeB/MgO structure by increasing the spin torque efficiency to an average of 3.0 kBT/µA for 37-nm-diameter junctions, about three times that of a MgO/CoFeB/Ta free layer, which makes it the highest value reported to date. By comparing two films with different RA, hence different switching voltage and power, we explore the contributions of heating and voltage-modulated anisotropy change to the switching properties.

A statistical study of magnetic tunnel junctions for high-density spin torque transfer-MRAM (STT-MRAM)

We have demonstrated a robust magnetic tunnel junction (MTJ) with a resistance-area product RA=8 Omega-mum2 that simultaneously satisfies the statistical requirements of high tunneling magnetoresistance TMR > 15sigma(Rp), write threshold spread sigma(Vw)/<Vw> <7.1%, breakdown-to-write voltage margin over 0.5 V, read-induced disturbance rate below 10-9, and sufficient write endurance, and is free of unwanted write-induced magnetic reversal. The statistics suggest that a 64 Mb chip at the 90-nm node is feasible.

Demonstration of fully functional 8Mb perpendicular STT-MRAM chips with sub-5ns writing for non-volatile embedded memories

We present major breakthroughs in MTJ design for STT-MRAM applications allowing reliable write for pulse lengths down to 1.5ns, data retention up to 125°C for 10 years and full compatibility with BEOL process up to 400°C for 1 hour. We have successfully integrated the novel structure onto an 8Mbit test chip. We demonstrate writing of every single cell in the array using sub-5ns pulses over a wide temperature range without using any error correction. We also show that sensing times of 4ns are sufficient to read every data cell. The inherent scalability of the design makes it a prime candidate for universal embedded non-volatile memories down to the 28nm node and beyond.

Solving the paradox of the inconsistent size dependence of thermal stability at device and chip-level in perpendicular STT-MRAM

Current understanding of thermal stability of perpendicular STT-MRAM based on device-level data suggests that the thermal stability factor A is almost independent of device diameter above ~30nm. Here we report that contrary to this conventional wisdom, chip-level data retention exhibits substantial size dependence for diameters between 55 and 100 nm. We show that the method widely used to measure A is inaccurate for devices larger than ~30 nm, leading to significant underestimation of the size dependence. We derive an improved model, allowing us to reconcile the size dependence of A measured at device and chip level.

Demonstration of chip level writability, endurance and data retention of an entire 8Mb STT-MRAM array

We demonstrate the writability of an entire 8 Mb STT-MRAM chip and present data on the expected endurance and data retention up to 90°C. The chip utilizes a device structure that displays high spin-transfer torque efficiency and proper write-current scaling, down to write pulse width of about 1.5 ns.

Achieving Sub-ns switching of STT-MRAM for future embedded LLC applications through improvement of nucleation and propagation switching mechanisms

We present recent advances in writing speed of pSTT_MRAM which demonstrate its potential as a candidate for replacement of LCC cache for advanced technology nodes as well as applications where non-volatility may be needed. In this paper we explore the feasibility of sub-ns switching of devices and their characterization using comprehensive time resolved electrical measurement of the reversal mechanism. We show that the switching mechanism can be described as a simple nucleation followed by propagation model that can be characterized statistically. We further demonstrate that after optimization of the Magnetic Tunnel Junction (MTJ) stack, single devices can be switched reliably using write pulse length down to 750ps while preserving functionality and data retention @ 125°C. Results of the integration at array level on an 8MB test vehicle are also presented allowing full array writing using 3ns pulses without ECC and demonstrated data retention of 10 years (1ppm) at 125°C.

Reliability study of perpendicular STT-MRAM as emerging embedded memory qualified for reflow soldering at 260°C

A comprehensive reliability analysis of perpendicular Spin-Transfer-Torque Magnetic Random Access Memory (pSTT-MRAM) is demonstrated that pSTT-MRAM is capable of fast write, more than 107 cycles endurance, less than 10-20 read disturb error rate at 125°C, and 10 years data retention up to 225°C at chip level. Furthermore, we prove for the first time that pSTT-MRAM technology can withstand reflow soldering at 260°C, thus enabling the opportunity for embedded nonvolatile memories in consumer and automotive Microcontrollers (MCUs) applications.

Demonstration of an MgO based anti-fuse OTP design integrated with a fully functional STT-MRAM at the Mbit level

STT-MRAM technology has been attracting renewed attention since the embedability of a working STT-MRAM design has been demonstrated [1]. In this paper we expand on the versatility of STT-MRAM by demonstrating the conversion of a standard STT-MRAM cell to a One Time Programmable (OTP) anti-fuse cell. Both designs are integrated at the Mbit level on a single chip using the same magnetic stack, processing and CMOS cell design. A single BEOL mask change can convert an STT-MRAM device to an OTP design by simply reducing its size. The increased resistance yields larger voltage drop across the device, due to the voltage divider effect in the 1T-1MTJ cell and is sufficient to trigger reliable dielectric breakdown of the oxide tunnel barrier, effectively shorting the device. In this paper we demonstrate the seamless integration of an OTP based on STT-MRAM and 100% programming and reading yield at the Mbit level.