Tomaso Poggi

Ultra-Fast Stabilizing Model Predictive Control via Canonical Piecewise Affine Approximations

This paper investigates the use of canonical piecewise affine (PWA) functions for approximation and fast implementation of linear MPC controllers. The control law is approximated in an optimal way over a regular simplicial partition of a given set of states of interest. The stability properties of the resulting closed-loop system are analyzed by constructing a suitable PWA Lyapunov function. The main advantage of the proposed approach to the implementation of MPC controllers is that the resulting stabilizing approximate MPC controller can be implemented on chip with sampling times in the order of tens of nanoseconds.

Digital architectures realizing piecewise-linear multivariate functions: Two FPGA implementations

Digital architectures for the circuit realization of multivariate piecewise-linear (PWL) functions are reviewed and compared. The output of the circuits is a digital word representing the value of the PWL function at the n-dimensional input. In particular, we propose two architectures with different levels of parallelism/complexity. PWL functions with n = 3 inputs are implemented on an FPGA and experimental results are shown. The accuracy in the representation of PWL functions is tested through three benchmark examples, two concerning three-variate static functions and one concerning a dynamical control system defined by a bi-variate PWL function. Copyright

Circuit implementation of piecewise-affine functions based on a binary search tree

In this paper we introduce a digital architecture implementing piecewise-affine functions defined over domains partitioned into polytopes: the functions are linear affine over each polytope. The polytope containing the input vector is found by exploring a previously constructed binary search tree. Once the polytope is detected, the function is evaluated by addressing an affine map whose coefficients are stored in a memory. The architecture has been implemented on FPGA and experimental results for a benchmark example are shown.

Digital Circuit Realization of Piecewise-Affine Functions With Nonuniform Resolution: Theory and FPGA Implementation

This brief proposes a digital circuit architecture implementing a class of continuous piecewise-affine (PWA) functions. The work rests on a previous architecture realizing PWA functions with uniform resolution. By using PWA mapping that can be implemented through a few simple functional blocks, it is possible to extend the representation capabilities of the architecture to PWA functions with nonuniform resolution. After defining the mapping and the corresponding functional blocks, the proposed architecture is implemented in a field-programmable gate array, and a simple example is shown.

High-Speed Piecewise Affine Virtual Sensors

This paper proposes piecewise affine (PWA) virtual sensors for the estimation of unmeasured variables of nonlinear systems with unknown dynamics. The estimation functions are designed directly from measured inputs and outputs and have two important features. First, they enjoy convergence and optimality properties, based on classical results on parametric identification. Second, the PWA structure is based on a simplicial partition of the measurement space and allows one to implement very effectively the virtual sensor on a digital circuit. Due to the low cost of the required hardware for the implementation of such a particular structure and to the very high sampling frequencies that can be achieved, the approach is applicable to a wide range of industrial problems.

Integrated circuit implementation of multi-dimensional piecewise-linear functions

In this paper we present an integrated circuit implementing piecewise-linear (PWL) functions with three inputs, where each input can be either analog or digital. The PWL function to be implemented can be chosen by properly storing a set of coefficients in a 4 kB external memory. Experimental results are shown that demonstrate the circuit working up to 50 MHz with a maximum power consumption of 3.7 mW. Measurements corresponding to both static and time-varying inputs are provided and discussed.

A Simplicial PWL Integrated Circuit Realization

In this paper we present a mixed-signal integrated circuit in a standard CMOS 0.5 µm technology implementing a piecewise-linear (PWL) function with three inputs, where each input can be either analog or coded with 8 bits. The output of the circuit is a digital word with 8-bit precision, representing the value of the PWL function at the three-dimensional input. The circuit accesses also a 4 kB external memory, which is addressed with a 12-bit word. Experimental results are shown that demonstrate the circuit working up to 50 MHz with a maximum power consumption of 3.7 mW.

FPGA implementation of a new scheme for the circuit realization of PWL functions

A new scheme for the circuit realization of multivariate PWL functions is proposed. A three-variate version is implemented on an FPGA board. A comparison with respect to another scheme, already implemented on chip, is provided, showing that the new scheme is more complex, but reduces the computation times. Two benchmark examples are considered to show the high accuracy of the circuit in the representation of PWL functions.

MOBY-DIC : a Matlab toolbox for circuit-oriented design of explicit MPC

This paper describes a MATLAB Toolbox for the integrated design of Model Predictive Control (MPC) state-feedback control laws and the digital circuits implementing them. Explicit MPC laws can be designed using optimal and sub-optimal formulations, directly taking into account the specifications of the digital circuit implementing the control law (such as latency and size), together with the usual control specifications (stability, performance, constraint satisfaction). Tools for a-posteriori stability analysis of the closed-loop system, and for the simulation of the circuit in Simulink, are also included in the toolbox.

Low-complexity piecewise-affine virtual sensors: theory and design

This paper is focused on the theoretical development and the hardware implementation of low-complexity piecewise-affine direct virtual sensors for the estimation of unmeasured variables of interest of nonlinear systems. The direct virtual sensor is designed directly from measured inputs and outputs of the system and does not require a dynamical model. The proposed approach allows one to design estimators which mitigate the effect of the so-called ‘curse of dimensionality’ of simplicial piecewise-affine functions, and can be therefore applied to relatively high-order systems, enjoying convergence and optimality properties. An automatic toolchain is also presented to generate the VHDL code describing the digital circuit implementing the virtual sensor, starting from the set of measured input and output data. The proposed methodology is applied to generate an FPGA implementation of the virtual sensor for the estimation of vehicle lateral velocity, using a hardware-in-the-loop setting.